Inventor profile of:

Scott Wu

City:

San Jose, California

Country:

United States

Published Applications:

15

Last publication date:

2019-08-08

Top Assignees for applications by Scott Wu

The entities that hold a legal rights for patent applications filed by inventor Wu Scott:

Recent patent applications by Wu Scott

Scott Wu from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-08-08
US20190242941A1
Physics

Methods and Apparatus for Testing an Integrated Circuit

#2 | 2018-12-13
US20180356444A1
Physics

Multi-test type probe card and corresponding testing system for parallel testing of dies via multiple test sites

#3 | 2016-06-02
US20160155732A1
Electricity

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

#4 | 2015-10-29
US20150311147A1
Electricity

SEMICONDUCTOR PACKAGE WITH A SEMICONDUCTOR DIE EMBEDDED WITHIN SUBSTRATES

#5 | 2015-10-01
US20150279806A1
Electricity

Recessed semiconductor substrates and associated techniques

#6 | 2015-08-13
US20150228569A1
Electricity

Method and apparatus for improving the reliability of a connection to a via in a substrate

#7 | 2014-05-15
US20140132296A1
Physics

Heat sink blade pack for device under test testing

#8 | 2014-05-08
US20140124961A1
Electricity

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

#9 | 2014-04-17
US20140106508A1
Electricity

Structures embedded within core material and methods of manufacturing thereof

#10 | 2012-03-01
US20120049364A1
Electricity

Structures embedded within core material and methods of manufacturing thereof

#11 | 2011-09-22
US20110227223A1
Electricity

Embedded die with protective interposer

#12 | 2011-08-04
US20110186998A1
Electricity

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

#13 | 2011-08-04
US20110186992A1
Electricity

Recessed semiconductor substrates and associated techniques

#14 | 2011-08-04
US20110186960A1
Electricity

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

#15 | 2011-05-26
US20110121444A1
Electricity

Semiconductor package with a semiconductor die embedded within substrates

InventorID:

728041 ⎘