Inventor profile of:

Shayak Banerjee

City:

Austin, Texas

Country:

United States

Published Applications:

22

Last publication date:

2019-11-07

Top Assignees for applications by Shayak Banerjee

The entities that hold a legal rights for patent applications filed by inventor Banerjee Shayak:

Recent patent applications by Banerjee Shayak

Shayak Banerjee from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-11-07
US20190340329A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#2 | 2019-08-22
US20190258774A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#3 | 2017-04-27
US20170116368A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#4 | 2016-07-07
US20160196502A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#5 | 2016-03-31
US20160092783A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#6 | 2015-07-30
US20150213374A1
Physics

Detecting hotspots using machine learning on diffraction patterns

#7 | 2015-04-23
US20150112649A1
Physics

Clustering Lithographic Hotspots Based on Frequency Domain Encoding

#8 | 2014-04-03
US20140095124A1
Physics

Optical rule checking for detecting at risk structures for overlay issues

#9 | 2014-03-13
US20140075397A1
Physics

Pitch-aware multi-patterning lithography

#10 | 2013-12-17
US13628278
-

Retargeting multiple patterned integrated circuit device designs

#11 | 2013-06-20
US20130159943A1
Physics

Machine learning approach to correct lithographic hot-spots

#12 | 2013-01-03
US20130003108A1
Physics

Frequency domain layout decomposition in double patterning lithography

#13 | 2012-12-13
US20120317523A1
Physics

Reducing through process delay variation in metal wires

#14 | 2012-06-07
US20120144356A1
Physics

Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance

#15 | 2012-02-16
US20120040280A1
Physics

Simultaneous optical proximity correction and decomposition for double exposure lithography

#16 | 2011-06-23
US20110154280A1
Physics

Propagating design tolerances to shape tolerances for lithography

#17 | 2011-06-23
US20110150343A1
Physics

Optical proximity correction for transistors using harmonic mean of gate length

#18 | 2011-05-19
US20110119642A1
Physics

Simultaneous photolithographic mask and target optimization

#19 | 2010-12-30
US20100333049A1
Physics

Model-based retargeting of layout patterns for sub-wavelength photolithography

#20 | 2010-10-21
US20100269079A1
Physics

Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance

#21 | 2010-05-13
US20100122231A1
Physics

Electrically-driven optical proximity correction to compensate for non-optical effects

#22 | 2009-08-06
US20090199151A1
Physics

Electrically driven optical proximity correction

InventorID:

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