Dallas, Texas
United States
129
2025-11-06
The entities that hold a legal rights for patent applications filed by inventor Chirca Kai:
Kai Chirca from Dallas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#2 | 2025-10-30Computational Primitives Using A Matrix Multiplication Accelerator
#3 | 2025-10-30BRANCH PREDICTION USING LOOP ITERATION COUNT
#4 | 2025-10-23MULTICORE SHARED CACHE OPERATION ENGINE
#5 | 2025-10-09CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#6 | 2025-10-02NESTED LOOP CONTROL
#7 | 2025-09-11SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES
#8 | 2025-07-17VIRTUAL NETWORK PRE-ARBITRATION
#9 | 2025-06-05MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#10 | 2025-05-08EXIT HISTORY BASED BRANCH PREDICTION
#11 | 2025-04-10NESTED LOOP CONTROL
#12 | 2025-03-27MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
#13 | 2025-03-20MULTICORE SHARED CACHE OPERATION ENGINE
#14 | 2025-02-20CONFIGURABLE CACHE FOR COHERENT SYSTEM
#15 | 2025-02-06BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM
#16 | 2025-01-09CACHE COHERENCE SHARED STATE SUPPRESSION
#17 | 2025-01-09STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
#18 | 2024-12-12PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
#19 | 2024-11-21CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
#20 | 2024-08-22NESTED LOOP CONTROL
#21 | 2024-08-08Computational Primitives Using A Matrix Multiplication Accelerator
#22 | 2024-06-13Memory pipeline control in a hierarchical memory system
#23 | 2024-06-06MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#24 | 2024-05-09Branch Prediction Using loop Iteration Count
#25 | 2024-04-30Nested loop control
#26 | 2024-04-18Software-hardware memory management modes
#27 | 2024-03-28SYSTEM AND METHOD FOR ADDRESSING DATA IN MEMORY
#28 | 2024-03-14Nested loop control
#29 | 2024-03-14DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#30 | 2024-02-01IMPLIED FENCE ON STREAM OPEN
#31 | 2023-12-28Multicore shared cache operation engine
#32 | 2023-11-30Configurable cache for coherent system
#33 | 2023-11-02MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED PIPELINE PROCESSOR
#34 | 2023-10-12Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#35 | 2023-09-21Cache coherence shared state suppression
#36 | 2023-06-15Memory pipeline control in a hierarchical memory system
#37 | 2023-06-15Streaming engine with deferred exception reporting
#38 | 2023-06-15USER MODE EVENT HANDLING
#39 | 2023-02-16SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
#40 | 2023-01-26PROGRAMMABLE EVENT TESTING
#41 | 2022-11-24Multicore, multibank, fully concurrent coherence controller
#42 | 2022-11-24CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#43 | 2022-11-17EVENT HANDLING IN PIPELINE EXECUTE STAGES
#44 | 2022-10-13Exit history based branch prediction
#45 | 2022-09-08DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#46 | 2022-08-25MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
#47 | 2022-08-18Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels
#48 | 2022-08-04Cache Preload Operations Using Streaming Engine
#49 | 2022-07-21Configurable cache for multi-endpoint heterogeneous coherent system
#50 | 2022-05-26Cache coherence shared state suppression
#51 | 2022-05-19Delayed snoop for improved multi-process false sharing parallel thread performance
#52 | 2022-05-19Multicore shared cache operation engine
#53 | 2022-05-05Processing device with a microbranch target buffer for branch prediction using loop iteration count
#54 | 2022-01-27Memory pipeline control in a hierarchical memory system
#55 | 2021-12-30Cache management operations using streaming engine
#56 | 2021-12-09Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#57 | 2021-11-18System and method for addressing data in memory
#58 | 2021-11-11Multi-processor bridge with cache allocate awareness
#59 | 2021-10-28Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA)
#60 | 2021-10-28Nested loop control
#61 | 2021-10-21MULTICORE SHARED CACHE OPERATION ENGINE
#62 | 2021-08-12Mechanism for interrupting and resuming execution on an unprotected pipeline processor
#63 | 2021-08-05Highly integrated scalable, flexible DSP megamodule architecture
#64 | 2021-07-15Implied fence on stream open
#65 | 2021-04-29Programmable event testing
#66 | 2021-04-29User mode event handling
#67 | 2021-04-29Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet
#68 | 2021-04-15Software-hardware memory management modes
#69 | 2021-01-28Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#70 | 2021-01-14Multicore bus architecture with non-blocking high performance transaction credit system
#71 | 2020-12-03Processing device with a microbranch target buffer for branch prediction using loop iteration count
#72 | 2020-11-26Memory pipeline control in a hierarchical memory system
#73 | 2020-11-26Cache coherence shared state suppression
#74 | 2020-11-26Streaming engine with deferred exception reporting
#75 | 2020-11-26System and method for addressing data in memory
#76 | 2020-11-26Nested loop control
#77 | 2020-11-26Nested loop control
#78 | 2020-09-24Flexible hybrid firewall architecture
#79 | 2020-09-10Cache preload operations using streaming engine
#80 | 2020-09-10Cache management operations using streaming engine
#81 | 2020-08-04Nested loop control
#82 | 2020-07-02Exit history based branch prediction
#83 | 2020-04-16Distributed error detection and correction with hamming code handoff
#84 | 2020-04-16Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#85 | 2020-04-16Credit aware central arbitration for multi-endpoint, multi-core system
#86 | 2020-04-16Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#87 | 2020-04-16Multi-power-domain bridge with prefetch and write merging
#88 | 2020-04-16Multicore, multibank, fully concurrent coherence controller
#89 | 2020-04-16Delayed snoop for improved multi-process false sharing parallel thread performance
#90 | 2020-04-16Multicore shared cache operation engine
#91 | 2020-04-16Configurable cache for multi-endpoint heterogeneous coherent system
#92 | 2020-04-16Multi-processor bridge with cache allocate awareness
#93 | 2020-04-16Multicore shared cache operation engine
#94 | 2019-11-21Multicore bus architecture with non-blocking high performance transaction credit system
#95 | 2019-08-08Mechanism for interrupting and resuming execution on an unprotected pipeline processor
#96 | 2019-07-18Implied fence on stream open
#97 | 2019-05-16Highly integrated scalable, flexible DSP megamodule architecture
#98 | 2019-03-28Cache preload operations using streaming engine
#99 | 2019-03-28Cache management operations using streaming engine
#100 | 2019-02-21Flexible hybrid firewall architecture
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