Kerry Bernstein

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

BEOL COMPATIBLE FET STRUCTURE

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Power supply for localized portions of an integrated circuit

Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof

Reactive metal optical security device and methods of fabrication and use

Inactivity triggered self clocking logic family

Double-sided integrated circuit chips

System and method for target-based compact modeling

Methods for normalizing strain in semicondcutor devices and strain normalized semiconductor devices

Semiconductor chip stacking for redundancy and yield improvement

BEOL compatible FET structrure

TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES

Test structure and methodology for three-dimensional semiconductor structures

Multi-wafer 3D CAM cell

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage

In-plane silicon heat spreader and method therefor

Double-sided integrated circuit chips

Double-sided integrated circuit chips

Deep trench capacitor for SOI CMOS devices for soft error immunity

SOI body contact using E-DRAM technology

Adaptive linesize in a cache

Power connector/decoupler integrated in a heat sink

Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch

Detecting chip alterations with light emission

System and method of masking electromagnetic interference (EMI) emissions of a circuit

Thermal switch for integrated circuits, design structure, and method of sensing temperature

Methods for normalizing strain in semiconductor devices and strain normalized semiconductor devices

FinFET transistor and circuit

Vertical through-silicon via for a semiconductor structure

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

SOI body contact using E-DRAM technology

Deep trench capacitor for SOI CMOS devices for soft error immunity

Double-sided integrated circuit chips

Soft error correction in sleeping processors

BEOL compatible FET structure

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Compact multi-port cam cell implemented in 3D vertical integration

CMOS back-gated keeper technique

Method and apparatus for dynamic measurement of across-chip temperatures

Processor pipeline architecture logic state retention systems and methods

Optimal local supply voltage determination circuit

CMOS back-gated keeper technique

Semiconductor chip stacking for redundancy and yield improvement

Soft error protection structure employing a deep trench

Back-gate decode personalization

Silicon heat spreader mounted in-plane with a heat source and method therefor

Design structure for implementing matrix-based search capability in content addressable memory devices

Apparatus and method for implementing matrix-based search capability in content addressable memory devices

Three-dimensional networking design structure

DUAL WIRED INTEGRATED CIRCUIT CHIPS

Double-sided integrated circuit chips

Test structure and methodology for three-dimensional semiconductor structures

Determining relative amount of usage of data retaining device based on potential of charge storing device

Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Three dimensional vertical E-fuse structures and methods of manufacturing the same

Testing for normal or reverse temperature related delay variations in integrated circuits

Dual-sided chip attached modules

Multicore processor having storage for core-specific operational data

Error correcting logic system

MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL

MULTI-WAFER 3D CAM CELL

Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator

Compact multi-port CAM cell implemented in 3D vertical integration

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Dual wired integrated circuit chips

Three-dimensional cascaded power distribution in a semiconductor device

THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS

Determining relative amount of usage of data retaining device based on potential of charge storing device

Dual wired integrated circuit chips

FinFET transistor and circuit

Wafer level I/O test, repair and/or customization enabled by I/O layer

Error correcting logic system

Method and architecture for power management of an electronic device

Three-dimensional cascaded power distribution in a semiconductor device

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement

Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof

Dual-sided chip attached modules

Double-sided integrated circuit chips

Dual wired integrated circuit chips

Three-dimensional networking structure

Determining relative amount of usage of data retaining device based on potential of charge storing device

Dual wired integrated circuit chips

Determining history state of data based on state of partially depleted silicon-on-insulator

Method and architecture for power management of an electronic device

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

Processor pipeline architecture logic state retention systems and methods

BEOL compatible FET structure

Wafer level I/O test and repair enabled by I/O layer

FinFET transistor and circuit

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement