Sovico
Italy
59
2026-03-12
The entities that hold a legal rights for patent applications filed by inventor Villa Corrado:
Corrado Villa from Sovico, IT has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY CELL ARRANGEMENT AND METHOD OF READING A CAPACITIVE MEMORY CELL
#2 | 2026-03-12MEMORY CELL ARRANGEMENT AND METHOD OF READING A CAPACITIVE MEMORY CELL
#3 | 2026-03-05MEMORY APPARATUS AND METHODS FOR ACCESSING AND MANUFACTURING THE SAME
#4 | 2025-03-13PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY
#5 | 2025-01-09DECODER ARCHITECTURE FOR MEMORY DEVICE
#6 | 2024-10-17VARIABLE PAGE SIZE ARCHITECTURE
#7 | 2024-01-04Providing power availability information to memory
#8 | 2023-06-08Memory device with data scrubbing capability and methods
#9 | 2023-04-13Systems and methods for adaptive self-referenced reads of memory devices
#10 | 2023-03-30Vertical 3D memory device and accessing method
#11 | 2023-02-02Wordline capacitance balancing
#12 | 2023-01-05Systems and methods for adaptive self-referenced reads of memory devices
#13 | 2022-12-15Decoder architecture for memory device
#14 | 2022-12-08Voltage equalization for pillars of a memory array
#15 | 2022-11-24MULTIPLY OPERATION CIRCUIT, MULTIPLY AND ACCUMULATE CIRCUIT, AND METHODS THEREOF
#16 | 2022-11-17MEMORY APPARATUS AND METHODS FOR ACCESSING AND MANUFACTURING THE SAME
#17 | 2022-07-21Variable page size architecture
#18 | 2022-06-09Voltage equalization for pillars of a memory array
#19 | 2022-06-02Decoder architecture for memory device
#20 | 2022-06-02Providing power availability information to memory
#21 | 2022-03-24MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME
#22 | 2022-03-10Vertical 3D memory device and method for manufacturing the same
#23 | 2021-10-28Wordline capacitance balancing
#24 | 2021-10-28Access schemes for activity-based data protection in a memory device
#25 | 2021-07-22Vertical 3D memory device and method for manufacturing the same
#26 | 2021-05-06Memory plate segmentation to reduce operating power
#27 | 2021-01-28Wordline capacitance balancing
#28 | 2021-01-21Providing power availability information to memory
#29 | 2021-01-14Power domain switches for switching power reduction
#30 | 2020-05-21Variable page size architecture
#31 | 2020-02-20Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations
#32 | 2020-01-30Memory plate segmentation to reduce operating power
#33 | 2019-11-07Providing power availability information to memory
#34 | 2019-08-08Apparatuses and methods for performing multiple memory operations
#35 | 2019-03-14Apparatuses and methods for memory operations having variable latencies
#36 | 2019-01-31Apparatuses and methods for performing multiple memory operations
#37 | 2019-01-24Memory plate segmentation to reduce operating power
#38 | 2019-01-10Apparatuses and methods for memory operations having variable latencies
#39 | 2018-04-19Providing power availability information to memory
#40 | 2018-02-01Variable page size architecture
#41 | 2017-10-26Apparatuses and methods for memory operations having variable latencies
#42 | 2017-10-26Apparatuses and methods for memory operations having variable latencies
#43 | 2017-06-08Providing power availability information to memory
#44 | 2016-12-01Apparatuses and methods for performing multiple memory operations
#45 | 2016-07-28Providing power availability information to memory
#46 | 2016-03-03Error correction code for unidirectional memory
#47 | 2015-12-03Providing power availability information to memory
#48 | 2015-11-12Apparatuses and methods for performing multiple memory operations
#49 | 2014-05-01Apparatuses and methods for memory operations having variable latencies
#50 | 2014-05-01Apparatuses and methods for memory operations having variable latencies
#51 | 2013-10-24Error correction code for unidirectional memory
#52 | 2010-12-02Method and devices for controlling power loss
#53 | 2010-07-01Error correction code for unidirectional memory
#54 | 2007-09-20Reduction of the time for executing an externally commanded transfer of data in an integrated device
#55 | 2007-02-15Nonvolatile memory device with multiple references and corresponding control method
#56 | 2006-12-12Non-volatile memory device
#57 | 2006-11-16Data storing method for a non-volatile memory cell array having an error correction code
#58 | 2005-03-03Redundancy scheme for a memory integrated circuit
#59 | 2005-01-20Full-swing wordline driving circuit
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