Los Gatos, California
United States
48
2026-03-26
The entities that hold a legal rights for patent applications filed by inventor Yip Aaron S.:
Aaron S. Yip from Los Gatos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SUB-BLOCK DEFINITION IN A MEMORY DEVICE USING SEGMENTED SOURCE PLATES
#2 | 2026-03-05SUB-BLOCK ERASE IN MEMORY DEVICES USING SEGMENTED SOURCE PLATES
#3 | 2026-01-22MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
#4 | 2026-01-08SEMICONDUCTOR DEVICE ASSEMBLIES WITH DISCRETE MEMORY ARRAYS AND CMOS DEVICES CONFIGURED FOR EXTERNAL CONNECTION
#5 | 2025-07-03INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE
#6 | 2025-05-15MEMORY DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED ELECTRONIC SYSTEMS
#7 | 2024-12-26BLOCK-ON-BLOCK MEMORY ARRAY ARCHITECTURE USING BI-DIRECTIONAL STAIRCASES
#8 | 2024-12-12MEMORY DEVICES INCLUDING CONTROL LOGIC REGIONS
#9 | 2024-12-05MEMORY DEVICES HAVING SIGNAL ROUTING STRUCTURES AT BONDING INTERFACES
#10 | 2024-11-28MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION
#11 | 2024-11-21USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCKS IN A MEMORY DEVICE
#12 | 2024-09-19CREATING SEGMENTED SOURCE PLATES FOR SUB-BLOCK DEFINITION IN A MEMORY DEVICE
#13 | 2024-09-19SUB-BLOCK DEFINITION IN A MEMORY DEVICE USING SEGMENTED SOURCE PLATES
#14 | 2024-02-29MICROELECTRONIC DEVICES WITH MIRRORED BLOCKS OF MULTI-SET STAIRCASED STADIUMS, AND RELATED SYSTEMS AND METHODS
#15 | 2023-05-25Memory devices with four data line bias levels
#16 | 2023-05-04Microelectronic devices including control logic regions
#17 | 2023-04-13Using non-segregated cells as drain-side select gates for sub-blocks in a memory device
#18 | 2023-03-23Microelectronic devices having a memory array region, a control logic region, and signal routing structures
#19 | 2023-02-23Independent plane architecture in a memory device
#20 | 2023-02-09Memory devices with four data line bias levels
#21 | 2022-07-28Block-on-block memory array architecture using bi-directional staircases
#22 | 2022-03-10Vertical string driver for memory array
#23 | 2022-02-17Microelectronic devices, electronic systems having a memory array region and a control logic region, and methods of forming microelectronic devices
#24 | 2022-01-20Microelectronic devices, related electronic systems, and methods of forming microelectronic devices
#25 | 2021-11-25Memory devices with user-defined tagging mechanism
#26 | 2021-11-18Apparatus for memory cell programming
#27 | 2021-09-16Block-on-block memory array architecture using bi-directional staircases
#28 | 2021-09-02Memory cell programming applying a programming pulse having different voltage levels
#29 | 2021-02-18Microelectronic devices and memory devices
#30 | 2020-11-12Memory devices with user-defined tagging mechanism
#31 | 2020-10-15Memories for decoding memory access addresses for access operations
#32 | 2020-02-13Apparatus and methods for decoding memory access addresses for access operations
#33 | 2019-11-07Memory cell programming with a program pulse having a plurality of different voltage levels
#34 | 2019-09-19Erasing memory cells
#35 | 2019-07-11Apparatuses and methods for generating probabilistic information with current integration sensing
#36 | 2019-02-28Erasing memory cells sequentially
#37 | 2018-10-18Memory cell programming with a programming pulse having plurality of different voltage levels
#38 | 2018-07-03Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells
#39 | 2018-05-17Access line management in a memory device
#40 | 2018-03-22Apparatuses and methods for generating probabilistic information with current integration sensing
#41 | 2017-11-16Memory cell programming using VgVt value
#42 | 2017-09-21Memory cell programming utilizing conditional enabling of memory cells
#43 | 2017-03-16Access line management in a memory device
#44 | 2017-03-07Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly under the staircase
#45 | 2016-03-24Access line management in a memory device
#46 | 2015-10-01Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
#47 | 2015-03-05Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
#48 | 2014-05-08Access line management in a memory device
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