Plano, Texas
United States
66
2025-03-20
The entities that hold a legal rights for patent applications filed by inventor Bosshart Patrick:
Patrick Bosshart from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
CONFIGURING A SWITCH FOR EXTRACTING PACKET HEADER FIELDS
#2 | 2025-03-20ALGORITHMIC TCAM BASED TERNARY LOOKUP
#3 | 2025-02-06PACKET HEADER FIELD EXTRACTION
#4 | 2023-10-26CONFIGURING A SWITCH FOR EXTRACTING PACKET HEADER FIELDS
#5 | 2023-09-21EXPANSION OF PACKET DATA WITHIN PROCESSING PIPELINE
#6 | 2023-04-27Algorithmic TCAM based ternary lookup
#7 | 2022-11-15Stateful processing unit with min/max capability
#8 | 2022-10-27Packet header field extraction
#9 | 2022-09-01CONFIGURING A SWITCH FOR EXTRACTING PACKET HEADER FIELDS
#10 | 2022-02-22Data plane for learning flows, collecting metadata regarding learned flows and exporting metadata regarding learned flows
#11 | 2022-02-08Configuring a switch for extracting packet header fields
#12 | 2022-01-27Expansion of packet data within processing pipeline
#13 | 2021-06-24Resilient hashing for forwarding packets
#14 | 2021-06-10Forwarding element data plane with computing parameter distributor
#15 | 2020-12-29Data plane error detection for ternary content-addressable memory (TCAM) of a forwarding element
#16 | 2020-12-22Data plane with flow learning circuit
#17 | 2020-11-03Multiple copies of stateful tables
#18 | 2020-09-08Multiple packet data container types for a processing pipeline
#19 | 2020-09-01Compiler and hardware interactions to reuse register fields in the data plane of a network forwarding element
#20 | 2020-08-13Expansion of packet data within processing pipeline
#21 | 2020-06-25DATA-PLANE STATEFUL PROCESSING UNITS IN PACKET PROCESSING PIPELINES
#22 | 2020-05-21Network forwarding element with data plane packet snapshotting capabilities
#23 | 2020-04-07Forwarding element with flow learning circuit in its data plane
#24 | 2020-03-26PACKET HEADER FIELD EXTRACTION
#25 | 2020-03-26Packet header field extraction
#26 | 2020-03-26Packet header field extraction
#27 | 2020-03-24Configurable packet processing pipeline for handling non-packet data
#28 | 2020-03-17Expansion of packet data within processing pipeline
#29 | 2020-03-05Packet header field extraction
#30 | 2019-12-24Error handling for match action unit memory of a forwarding element
#31 | 2019-12-17Network forwarding element with data plane packet snapshotting capabilities
#32 | 2019-10-22Pipeline chaining
#33 | 2019-10-01Packet header field extraction
#34 | 2019-08-01Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element
#35 | 2019-08-01Algorithmic TCAM based ternary lookup
#36 | 2019-08-01Coding scheme for indirect addressing of multiple action memories
#37 | 2019-06-13Algorithmic TCAM based ternary lookup
#38 | 2019-06-04Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element
#39 | 2019-06-04Resilient hashing for forwarding packets
#40 | 2019-05-28Data plane error detection for ternary content-addressable memory (TCAM) of a forwarding element
#41 | 2019-04-23Proxy hash table
#42 | 2019-03-05Configuring a switch for extracting packet header fields
#43 | 2018-11-13Error handling for match action unit memory of a forwarding element
#44 | 2018-09-18Dynamic memory reallocation for match-action packet processing
#45 | 2018-08-23Coding scheme for indirect addressing of multiple action memories
#46 | 2018-08-16DATA-PLANE STATEFUL PROCESSING UNITS IN PACKET PROCESSING PIPELINES
#47 | 2018-06-21Coding scheme for identifying location of action entries
#48 | 2017-03-30Data-plane stateful processing units in packet processing pipelines
#49 | 2017-03-02Configuring a switch for extracting packet header fields
#50 | 2017-03-02Packet header field extraction
#51 | 2016-08-25Virtual addresses for action memories of a hardware forwarding element
#52 | 2016-08-25Coding scheme for indirect addressing of multiple action memories
#53 | 2016-08-25Addressing match and action entries in a match-action stage
#54 | 2016-08-25Coding scheme for identifying location of action entries
#55 | 2016-07-28Dynamic memory reallocation for match-action packet processing
#56 | 2016-04-07Fast adjusting load balancer
#57 | 2016-04-07Proxy hash table
#58 | 2014-05-08Reduced complexity hashing
#59 | 2012-12-20REDUCED CROSSTALK WIRING DELAY EFFECTS THROUGH THE USE OF A CHECKERBOARD PATTERN OF INVERTING AND NONINVERTING REPEATERS
#60 | 2009-10-22Decision feedback equalizer having parallel processing architecture
#61 | 2009-07-02High performance clocked latches and devices therefrom
#62 | 2009-07-02HIGH PERFORMANCE LATCHES
#63 | 2009-07-02INTEGRATED CIRCUITS HAVING DEVICES IN ADJACENT STANDARD CELLS COUPLED BY THE GATE ELECTRODE LAYER
#64 | 2009-07-02High performance pulsed buffer
#65 | 2006-02-09Methods and systems to reduce data skew in FIFOs
#66 | 2005-11-29Crossbar circuit having a plurality of repeaters forming different repeater arrangements
756542 ⎘