Yang Du

Ultra-low power neuromorphic artificial intelligence computing accelerator

Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

Diode-based temperature sensor

Ultra-low power neuromorphic artificial intelligence computing accelerator

POWER DISTRIBUTION NETWORKS FOR A THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC)

Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)

Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods

DYNAMICALLY CONTROLLING VOLTAGE PROVIDED TO THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) TO ACCOUNT FOR PROCESS VARIATIONS MEASURED ACROSS INTERCONNECTED IC TIERS OF 3DICs

Connection propagation for inter-logical block connections in integrated circuits

Graphene NMOS transistor using nitrogen dioxide chemical adsorption

Bondable device including a hydrophilic layer

Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)

Process variation power control in three-dimensional (3D) integrated circuits (ICs) (3DICs)

Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology

Power delivery network (PDN) design for monolithic three-dimensional (3-D) integrated circuit (IC)

MULTI-LEVEL CONVERSION FLIP-FLOP CIRCUITS FOR MULTI-POWER DOMAIN INTEGRATED CIRCUITS (ICs) AND RELATED METHODS

CLOCK TREE DESIGN METHODS FOR ULTRA-WIDE VOLTAGE RANGE CIRCUITS

Dual power swing pipeline design with separation of combinational and sequential logics

Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems

Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits

Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits

METHODS FOR CONSTRUCTING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS

Memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms

Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3D IC) integration

HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS

Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs)

Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems

PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC

Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods

TRANSISTORS WITH IMPROVED THERMAL CONDUCTIVITY

Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and methods

Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace

ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS

Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components

METHODS OF DESIGNING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS AND COMPONENTS

LASER ANNEALING METHODS FOR INTEGRATED CIRCUITS (ICs)

Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods

DIGITAL TEMPERATURE ESTIMATORS (DTEs) DISPOSED IN INTEGRATED CIRCUITS (ICs) FOR ESTIMATING TEMPERATURE WITHIN THE ICs, AND RELATED SYSTEMS AND METHODS

Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology

Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods

MONOLITHIC THREE DIMENSIONAL (3D) RANDOM ACCESS MEMORY (RAM) ARRAY ARCHITECTURE WITH BITCELL AND LOGIC PARTITIONING

Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods

Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods

Monolithic three dimensional integration of semiconductor integrated circuits

Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods

ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS

3D floorplanning using 2D and 3D blocks

Data transfer across power domains

Clock distribution network for 3D integrated circuit

Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

High-speed high-power semiconductor devices

Method and apparatus for estimating resistance and capacitance of metal interconnects