Inventor profile of:

Jing LI

City:

Ossining, New York

Country:

United States

Published Applications:

30

Last publication date:

2015-01-29

Top Assignees for applications by Jing LI

The entities that hold a legal rights for patent applications filed by inventor LI Jing:

Recent patent applications by LI Jing

Jing LI from Ossining, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-01-29
US20150032979A1
Physics

Self-adjusting phase change memory storage module

#2 | 2015-01-01
US20150004800A1
Electricity

Self-aligned patterning technique for semiconductor device features

#3 | 2015-01-01
US20150004785A1
Electricity

Self-aligned patterning technique for semiconductor device features

#4 | 2015-01-01
US20150001459A1
Electricity

Phase change memory cell with large electrode contact area

#5 | 2014-09-18
US20140281294A1
Physics

Adaptive reference tuning for endurance enhancement of non-volatile memories

#6 | 2014-09-18
US20140281162A1
Physics

Adaptive reference tuning for endurance enhancement of non-volatile memories

#7 | 2014-09-18
US20140264557A1
Electricity

SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS

#8 | 2014-09-18
US20140264497A1
Electricity

SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS

#9 | 2014-09-11
US20140256100A1
Electricity

Electrical coupling of memory cell access devices to a word line

#10 | 2014-09-11
US20140252556A1
Electricity

SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES

#11 | 2014-09-11
US20140252418A1
Electricity

Electrical coupling of memory cell access devices to a word line

#12 | 2014-08-26
US13931803
-

Vertical surround gate formation compatible with CMOS integration

#13 | 2014-06-19
US20140170831A1
Electricity

Phase change memory cell with large electrode contact area

#14 | 2014-06-19
US20140166962A1
Electricity

Phase change memory cell with large electrode contact area

#15 | 2014-04-03
US20140092694A1
Physics

Multi-bit resistance measurement

#16 | 2014-02-20
US20140052901A1
Physics

Method of reducing system power with mixed cell memory array

#17 | 2014-02-20
US20140052900A1
Physics

Memory controller for memory with mixed cell array and method of controlling the memory

#18 | 2014-02-20
US20140052895A1
Physics

Memory with mixed cell array and system including the memory

#19 | 2014-02-20
US20140052894A1
Physics

Memory controller for memory with mixed cell array and method of controlling the memory

#20 | 2014-02-18
US13783388
-

Single-mask spacer technique for semiconductor device features

#21 | 2014-01-23
US20140026008A1
Physics

Writing scheme for phase change material-content addressable memory

#22 | 2014-01-23
US20140022851A1
Physics

Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming

#23 | 2014-01-23
US20140022850A1
Physics

Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming

#24 | 2013-11-28
US20130314983A1
Physics

Drift-insensitive or invariant material for phase change memory

#25 | 2013-11-28
US20130313501A1
Physics

Drift-insensitive or invariant material for phase change memory

#26 | 2013-10-15
US13587146
-

Writing scheme for phase change material-content addressable memory

#27 | 2013-08-29
US20130223125A1
Physics

Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming

#28 | 2013-08-29
US20130223121A1
Physics

Sense scheme for phase change material content addressable memory

#29 | 2013-02-07
US20130033915A1
Physics

Content addressable memories with wireline compensation

#30 | 2012-03-15
US20120063195A1
Physics

Reconfigurable multi-level sensing scheme for semiconductor memories

InventorID:

76786 ⎘