James D. Warnock

Pessimism reduction in cross-talk noise determination used in integrated circuit design

Operating pulsed latches on a variable power supply

Priority based circuit synthesis

Operating pulsed latches on a variable power supply

Adjusting scan connections based on scan control locations

Programmable integrated circuit standard cell

Programmable integrated circuit standard cell

Programmable clock division methodology with in-context frequency checking

Early analysis and mitigation of self-heating in design flows

Programmable clock division methodology with in-context frequency checking

Initializing scannable and non-scannable latches from a common clock buffer

Initializing scannable and non-scannable latches from a common clock buffer

Adjusting scan connections based on scan control locations

Priority based circuit synthesis

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

Debugging scan latch circuits using flip devices

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Debugging scan latch circuits using flip devices

Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network

Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Validating variation of timing constraint measurements

Validating variation of timing constraint measurements

Debugging scan latch circuits using flip devices

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

Signal distribution in integrated circuit using optical through silicon via

Signal distribution in integrated circuit using optical through silicon via

Margin improvement for configurable local clock buffer

Optimal spare latch selection for metal-only ECOs

Power grid generation through modification of an initial power grid based on power grid analysis

Clock skew analysis and optimization

CONTINUOUS VIA FOR POWER GRID

CONTINUOUS VIA FOR POWER GRID

Device-based random variability modeling in timing analysis

Apparatus and method for hardening latches in SOI CMOS devices

Low-power multi-output local clock buffer

LSSD compatibility for GSD unified global clock buffers

Apparatus and method for hardening latches in SOI CMOS devices

Structure for Transmission Gate Multiplexer

Transmission gate multiplexer

Transmission gate multiplexer

Structure for a configurable low power high fan-in multiplexer

Method and apparatus for a configurable low power high fan-in multiplexer

Leakage power estimation

Programmable local clock buffer

Pulsed local clock buffer (LCB) characterization ring oscillator

Scannable dynamic logic latch circuit

PARAMETERIZED SEMICONDUCTOR CHIP CELLS AND OPTIMIZATION OF THE SAME

High-speed level sensitive scan design test scheme with pipelined test clocks

Parallel field effect transistor structure having a body contact

METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR

Methods for modeling latch transparency

Methods for modeling latch transparency