Schoenaich
Germany
33
2018-12-27
The entities that hold a legal rights for patent applications filed by inventor Wendel Dieter:
Dieter Wendel from Schoenaich, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Current-mode sense amplifier
#2 | 2017-11-02Current-mode sense amplifier
#3 | 2017-08-24Structure for reducing pre-charge voltage for static random-access memory arrays
#4 | 2017-02-16Structure for reducing pre-charge voltage for static random-access memory arrays
#5 | 2017-02-16Structure for reducing pre-charge voltage for static random-access memory arrays
#6 | 2017-02-16Structure for reducing pre-charge voltage for static random-access memory arrays
#7 | 2016-12-15Current-mode sense amplifier
#8 | 2016-08-30Structure for reducing pre-charge voltage for static random-access memory arrays
#9 | 2016-04-28Signal distribution in integrated circuit using optical through silicon via
#10 | 2016-04-28Signal distribution in integrated circuit using optical through silicon via
#11 | 2016-03-10Current-mode sense amplifier
#12 | 2015-01-08Ball grid array configuration for reliable testing
#13 | 2015-01-08Ball grid array configuration for reliable testing
#14 | 2014-05-22Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages
#15 | 2011-05-05Apparatus and method for hardening latches in SOI CMOS devices
#16 | 2010-11-30Method and system for pipeline reduction
#17 | 2009-11-19Method to reduce leakage of a SRAM-array
#18 | 2009-05-28System and method for scanning sequential logic elements
#19 | 2009-05-28Apparatus and method for hardening latches in SOI CMOS devices
#20 | 2009-05-07Circuit design methodology to reduce leakage power
#21 | 2008-06-05Permute unit and method to operate a permute unit
#22 | 2008-03-27PARAMETERIZED SEMICONDUCTOR CHIP CELLS AND OPTIMIZATION OF THE SAME
#23 | 2007-06-05Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture
#24 | 2007-05-31Method and an integrated circuit for performing a test
#25 | 2007-03-15Scan chain disable function for power saving
#26 | 2006-05-04Scan chain disable function for power saving
#27 | 2005-08-09Low skew, power efficient local clock signal generation system
#28 | 2005-07-12Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments
#29 | 2005-06-28Method for verifying cross-sections
#30 | 2005-06-23Memory array with multiple read ports
#31 | 2005-03-31Methods for modeling latch transparency
#32 | 2005-03-31Methods for modeling latch transparency
#33 | 2005-01-13Pulse-width limited chip clock design
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