Inventor profile of:

Ronald Hall

City:

Cedar Park, Texas

Country:

United States

Published Applications:

16

Last publication date:

2016-07-28

Top Assignees for applications by Ronald Hall

The entities that hold a legal rights for patent applications filed by inventor Hall Ronald:

Recent patent applications by Hall Ronald

Ronald Hall from Cedar Park, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-07-28
US20160216970A1
Physics

Buffering instructions of a single branch, backwards short loop within a virtual loop buffer

#2 | 2014-05-22
US20140143521A1
Physics

Instruction swap for patching problematic instructions in a microprocessor

#3 | 2012-06-21
US20120159125A1
Physics

Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer

#4 | 2009-04-30
US20090113192A1
Physics

Efficiency of short loop instruction fetch

#5 | 2009-04-30
US20090113191A1
Physics

Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer

#6 | 2009-03-19
US20090077352A1
Physics

Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

#7 | 2009-02-12
US20090043997A1
Physics

Time-of-life counter for handling instruction flushes from a queue

#8 | 2008-12-04
US20080301374A1
Physics

Structure for dynamic livelock resolution with variable delay memory access queue

#9 | 2008-09-18
US20080229078A1
Physics

Dynamic power management in a processor design

#10 | 2008-07-10
US20080168261A1
Physics

Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor

#11 | 2008-03-13
US20080065873A1
Physics

DYNAMIC LIVELOCK RESOLUTION WITH VARIABLE DELAY MEMORY ACCESS QUEUE

#12 | 2007-04-12
US20070083742A1
Physics

Time-of-life counter design for handling instruction flushes from a queue

#13 | 2007-04-12
US20070083734A1
Physics

Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor

#14 | 2007-03-29
US20070074059A1
Physics

Dynamic power management in a processor design

#15 | 2007-01-25
US20070022278A1
Physics

Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

#16 | 2005-03-10
US20050055506A1
Physics

Pseudo-LRU for a locking cache

InventorID:

773565 ⎘