Inventor profile of:

Thomas Strach

City:

Wildberg

Country:

Germany

Published Applications:

19

Last publication date:

2020-06-25

Top Assignees for applications by Thomas Strach

The entities that hold a legal rights for patent applications filed by inventor Strach Thomas:

Recent patent applications by Strach Thomas

Thomas Strach from Wildberg, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-06-25
US20200201413A1
Physics

Fine resolution on-chip voltage simulation to prevent under voltage conditions

#2 | 2020-06-25
US20200201407A1
Physics

Predictive on-chip voltage simulation to detect near-future under voltage conditions

#3 | 2020-01-30
US20200033927A1
Physics

Distributed on chip network to mitigate voltage droops

#4 | 2019-10-29
US16196080
Electricity

Mitigating power noise using a current supply

#5 | 2019-09-26
US20190295938A1
Electricity

Discrete electronic device embedded in chip module

#6 | 2018-08-09
US20180228028A1
Electricity

Discrete electronic device embedded in chip module

#7 | 2018-04-19
US20180107771A1
Physics

Layout effect characterization for integrated circuits

#8 | 2018-03-29
US20180088650A1
Physics

Distributed on chip network to mitigate voltage droops

#9 | 2018-02-27
US15594782
Physics

Layout effect characterization for integrated circuits

#10 | 2018-02-22
US20180052200A1
Physics

Increasing the resolution of on-chip measurement circuits

#11 | 2018-01-25
US20180027659A1
Electricity

Discrete electronic device embedded in chip module

#12 | 2017-08-22
US15292422
Physics

Layout effect characterization for integrated circuits

#13 | 2017-06-06
US15214565
Electricity

Discrete electronic device embedded in chip module

#14 | 2017-01-05
US20170004248A1
Physics

De-coupling capacitance placement

#15 | 2017-01-05
US20170004239A1
Physics

De-coupling capacitance placement

#16 | 2014-10-23
US20140316725A1
Physics

Power noise histogram of a computer system

#17 | 2014-06-05
US20140157277A1
Physics

Reducing power grid noise in a processor while minimizing performance loss

#18 | 2014-06-05
US20140157033A1
Physics

Reducing power grid noise in a processor while minimizing performance loss

#19 | 2007-01-25
US20070022398A1
Electricity

Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules

InventorID:

790041 ⎘