Hsinchu
Taiwan
169
2025-10-16
The entities that hold a legal rights for patent applications filed by inventor LEE Cheng Hung:
Cheng Hung LEE from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY DEVICE SENSE AMPLIFIER CONTROL
#2 | 2025-10-09MEMORY DEVICE AND METHOD FOR REDUCING ACTIVE POWER CONSUMPTION THEREOF USING ADDRESS CONTROL
#3 | 2025-09-25MEMORY DEVICE WITH WORD LINE PULSE RECOVERY
#4 | 2025-07-31REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS
#5 | 2025-07-03DUAL RAIL MEMORY DEVICE
#6 | 2025-05-22MEMORY DEVICE, WRITE ASSIST CIRCUIT, AND METHOD
#7 | 2025-05-22MEMORY CIRCUIT AND METHOD OF OPERATING SAME
#8 | 2025-04-24MEMORY DEVICE
#9 | 2025-03-13SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING
#10 | 2025-01-02POWER LOSS REGULATION CIRCUIT
#11 | 2024-12-12MEMORY DEVICE AND METHOD FOR REDUCING ACTIVE POWER CONSUMPTION THEREOF USING ADDRESS CONTROL
#12 | 2024-11-28Static Random Access Memory With Pre-Charge Circuit
#13 | 2024-11-21MEMORY DEVICE AND METHOD OF OPERATING THE SAME
#14 | 2024-10-24NEW WAS CELL FOR SRAM HIGH-R ISSUE IN ADVANCED TECHNOLOGY NODE
#15 | 2024-10-24MEMORY CIRCUITS WITH DYNAMICALLY ADJUSTABLE PULSE WIDTHS AND METHODS FOR OPERATING THE SAME
#16 | 2024-06-27I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS
#17 | 2024-06-20HEADER CIRCUIT PLACEMENT IN MEMORY DEVICE
#18 | 2024-05-23Latch circuit formed by modified memory cells
#19 | 2024-05-16MEMORY DEVICE WITH WORD LINE PULSE RECOVERY
#20 | 2024-03-21MEMORY DEVICE SENSE AMPLIFIER CONTROL
#21 | 2023-12-21Memory device and electronic device
#22 | 2023-12-21Memory circuit and method of operating same
#23 | 2023-11-30STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
#24 | 2023-11-30ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES
#25 | 2023-11-23Reducing internal node loading in combination circuits
#26 | 2023-11-09Was cell for SRAM high-R issue in advanced technology node
#27 | 2023-10-05VOLTAGE SUPPLY SELECTION CIRCUIT
#28 | 2023-09-07MEMORY DEVICE AND METHOD OF OPERATING THE SAME
#29 | 2023-08-03Power loss regulation circuit
#30 | 2023-04-27Header circuit placement in memory device
#31 | 2023-03-02Write assist cell for static random access memory
#32 | 2023-02-23Voltage supply selection circuit
#33 | 2022-12-27Header circuit placement in memory device
#34 | 2022-11-17Reducing internal node loading in combination circuits
#35 | 2022-11-10Arrangements of memory devices and methods of operating the memory devices
#36 | 2022-10-06Memory device and electronic device
#37 | 2022-09-29Computation apparatus and method using the same
#38 | 2022-08-25Memory device with word line pulse recovery
#39 | 2022-08-11Clock circuit and method of operating the same
#40 | 2022-08-11Reducing internal node loading in combination circuits
#41 | 2022-07-28Configurable memory storage system
#42 | 2022-03-17STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
#43 | 2022-03-03Memory device with word line pulse recovery
#44 | 2022-03-03Memory circuit, electronic device having the memory circuit, and method of operating memory circuit
#45 | 2021-10-28Level shifter
#46 | 2021-10-21Word line pulse width control circuit in static random access memory
#47 | 2021-09-16Memory macro and method of operating the same
#48 | 2021-09-02Semiconductor device having an inter-layer via (ILV), and method of making same
#49 | 2021-07-22I/O circuit design for SRAM-based PUF generators
#50 | 2021-07-01Clock circuit and method of operating the same
#51 | 2021-07-01Latch circuit
#52 | 2021-07-01Configurable memory storage system
#53 | 2021-04-29Power management circuit in memory device
#54 | 2021-04-22Memory device and electronic device
#55 | 2021-02-11Memory circuit and method of operating same
#56 | 2020-12-31Level shifter
#57 | 2020-12-29Operation assist circuit, memory device and operation assist method
#58 | 2020-12-17Method of fabricating a semiconductor device
#59 | 2020-12-10Leakage pathway prevention in a memory storage device
#60 | 2020-09-03Word line pulse width control circuit in static random access memory
#61 | 2020-07-23Level shifter
#62 | 2020-06-18Clock circuit and method of operating the same
#63 | 2020-06-04Memory macro and method of operating the same
#64 | 2020-04-30I/O circuit design for SRAM-based PUF generators
#65 | 2020-04-16Power switch control in a memory device
#66 | 2020-04-09Semiconductor memory device using shared data line for read/write operation
#67 | 2020-03-12Configurable memory storage system
#68 | 2020-02-13Level shifter
#69 | 2020-01-16Memory device and electronic device
#70 | 2020-01-16Latch circuit formed from bit cell
#71 | 2020-01-16Balanced coupling structure for physically unclonable function (PUF) application
#72 | 2020-01-16Power switch control for dual power supply
#73 | 2020-01-02Memory circuit and method of operating same
#74 | 2020-01-02Leakage pathway prevention in a memory storage device
#75 | 2019-10-24Method of fabricating a semiconductor device
#76 | 2019-08-22Memory macro and method of operating the same
#77 | 2019-08-15Power switch control for dual power supply
#78 | 2019-04-04Clock circuit and method of operating the same
#79 | 2019-03-28Semiconductor device having an inter-layer via (ILV), and method of making same
#80 | 2019-01-31Clock generating circuit and method of operating the same
#81 | 2019-01-03Power switch control for dual power supply
#82 | 2019-01-03Configurable memory storage system
#83 | 2018-11-29Read margin tracking in memory applications
#84 | 2018-11-29Word line pulse width control circuit in static random access memory
#85 | 2018-11-22Semiconductor memory device using shared data line for read/write operation
#86 | 2018-10-11Memory macro and method of operating the same
#87 | 2018-04-26Modified design rules to improve device performance
#88 | 2018-02-22Memory macro and method of operating the same
#89 | 2017-11-30Latch with built-in level shifter
#90 | 2017-09-28Memory macro and method of operating the same
#91 | 2017-09-21Level shifter
#92 | 2017-08-24Dual rail memory, memory macro and associated hybrid power supply method
#93 | 2017-05-25SRAM device capable of working in multiple low voltages without loss of performance
#94 | 2017-03-23Dual rail memory, memory macro and associated hybrid power supply method
#95 | 2017-02-28SRAM device capable of working in multiple low voltages without loss of performance
#96 | 2017-02-16Device having an inter-layer via (ILV), and method of making same
#97 | 2017-02-09Power management circuit for an electronic device
#98 | 2017-01-19Write driver and level shifter having shared transistors
#99 | 2016-08-18Pulling devices for driving data lines
#100 | 2016-05-12Integrated circuit having voltage mismatch reduction
8017 ⎘