Inventor profile of:

Yong Lu

City:

Rosemount, Minnesota

Country:

United States

Published Applications:

38

Last publication date:

2014-01-16

Top Assignees for applications by Yong Lu

The entities that hold a legal rights for patent applications filed by inventor Lu Yong:

Recent patent applications by Lu Yong

Yong Lu from Rosemount, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2014-01-16
US20140015075A1
Electricity

Magnetic memory with separate read and write paths

#2 | 2013-01-03
US20130003448A1
Physics

MRAM diode array and access method

#3 | 2012-09-13
US20120230094A1
Physics

Bit line charge accumulation sensing for resistive changing memory

#4 | 2012-09-13
US20120230093A1
Physics

Transmission gate-based spin-transfer torque memory unit

#5 | 2012-02-16
US20120039113A1
Electricity

Three dimensionally stacked non volatile memory units

#6 | 2012-02-16
US20120037875A1
Electricity

Mirrored-gate cell for non-volatile memory

#7 | 2011-09-22
US20110228598A1
Physics

Transmission gate-based spin-transfer torque memory unit

#8 | 2011-08-11
US20110194330A1
Physics

Memory array with read reference voltage cells

#9 | 2011-06-09
US20110134682A1
Physics

Variable write and read methods for resistive random access memory

#10 | 2011-04-21
US20110089509A1
Electricity

Magnetic memory with separate read and write paths

#11 | 2011-03-10
US20110058409A1
Physics

MRAM diode array and access method

#12 | 2010-10-21
US20100265749A1
Electricity

Three dimensionally stacked non volatile memory units

#13 | 2010-09-23
US20100238712A1
Physics

Variable write and read methods for resistive random access memory

#14 | 2010-09-16
US20100232211A1
Physics

Memory array with read reference voltage cells

#15 | 2010-08-19
US20100207219A1
Electricity

Single line MRAM

#16 | 2010-08-12
US20100202191A1
Physics

nvSRAM having variable magnetic resistors

#17 | 2010-06-03
US20100135066A1
Physics

Bit line charge accumulation sensing for resistive changing memory

#18 | 2010-05-20
US20100124352A1
Electricity

MICRO MAGNETIC DEVICE WITH MAGNETIC SPRING

#19 | 2010-05-13
US20100118602A1
Physics

DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF

#20 | 2010-05-13
US20100117121A1
Electricity

Mirrored-gate cell for non-volatile memory

#21 | 2010-04-15
US20100095050A1
Physics

Computer memory device with status register

#22 | 2010-04-15
US20100091562A1
Physics

Temperature dependent system for reading ST-RAM

#23 | 2010-04-15
US20100091546A1
Physics

HIGH DENSITY RECONFIGURABLE SPIN TORQUE NON-VOLATILE MEMORY

#24 | 2010-03-18
US20100067282A1
Physics

Memory array with read reference voltage cells

#25 | 2010-03-18
US20100067281A1
Physics

Variable write and read methods for resistive random access memory

#26 | 2010-03-04
US20100058125A1
Physics

Data devices including multiple error correction codes and methods of utilizing

#27 | 2010-02-11
US20100032778A1
Electricity

Magnetic memory with separate read and write paths

#28 | 2010-01-14
US20100008134A1
Physics

Transmission gate-based spin-transfer torque memory unit

#29 | 2008-05-13
US11464049
-

State save-on-power-down using GMR non-volatile elements

#30 | 2006-08-15
US10992052
-

State save-on-power-down using GMR non-volatile elements

#31 | 2005-12-06
US10637145
-

State save-on-power-down using GMR non-volatile elements

#32 | 2005-10-13
US20050226040A1
Electricity

Method for forming magneto-resistive memory cells with shape anisotropy

#33 | 2005-10-13
US20050226039A1
Physics

Magneto-resistive memory cell structures with improved selectivity

#34 | 2005-07-19
US10804584
-

Magneto-resistive memory cell structures with improved selectivity

#35 | 2005-06-14
US10886958
-

Magneto-resistive memory cell with shape anistropy and memory device thereof

#36 | 2005-05-03
US10677803
-

Magnetoresistive random access memory (MRAM) cell patterning

#37 | 2005-04-28
US20050088876A1
Physics

Bridge-type magnetic random access memory (MRAM) latch

#38 | 2005-03-08
US10775582
-

Bridge-type magnetic random access memory (MRAM) latch

InventorID:

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