Mountain View, California
United States
82
2023-07-18
The entities that hold a legal rights for patent applications filed by inventor Meixner Albert:
Albert Meixner from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Methods and apparatus for providing redundant networking capabilities for teleoperations
#2 | 2022-06-30MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR
#3 | 2021-12-09Image quality enhancement for autonomous vehicle remote operations
#4 | 2021-08-19Way partitioning for a system-level cache
#5 | 2021-06-03Two dimensional masked shift instruction
#6 | 2021-02-11Large lookup tables for an image processor
#7 | 2021-01-07Convolutional neural network on programmable two dimensional image processor
#8 | 2021-01-07Energy efficient processor core architecture for image processor
#9 | 2020-08-27Line buffer unit for image processor
#10 | 2020-08-13Image processor complex transfer functions
#11 | 2020-08-13Way partitioning for a system-level cache
#12 | 2020-06-25Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#13 | 2020-06-11Sheet generator for image processor
#14 | 2020-05-28Configurable and programmable image processor unit
#15 | 2020-05-21Macro I/O unit for image processor
#16 | 2020-05-21Circuit to perform dual input value absolute value and sum operation
#17 | 2020-05-14Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
#18 | 2020-04-16Virtual linebuffers for image signal processors
#19 | 2020-03-26Determination of per line buffer unit memory allocation
#20 | 2020-02-13Program code transformations to improve image processor runtime efficiency
#21 | 2020-02-13Configuration of application software on multi-core image processor
#22 | 2020-02-04Image processor complex transfer functions
#23 | 2020-01-16COMPILER TECHNIQUES FOR MAPPING PROGRAM CODE TO A HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING HARDWARE PLATFORM
#24 | 2019-12-12Architecture for high performance, power efficient, programmable image processing
#25 | 2019-11-28Two dimensional shift array for image processor
#26 | 2019-10-24Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
#27 | 2019-10-24Line buffer unit for image processor
#28 | 2019-08-01Virtual linebuffers for image signal processors
#29 | 2019-07-18Energy efficient processor core architecture for image processor
#30 | 2019-07-11MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR
#31 | 2019-07-04Sheet generator for image processor
#32 | 2019-06-20Compiler managed memory for image processor
#33 | 2019-01-03Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#34 | 2018-11-15Determination of per line buffer unit memory allocation
#35 | 2018-11-15Configurable and programmable image processor unit
#36 | 2018-11-15Image processor with high throughput internal communication protocol
#37 | 2018-11-15Image processor with configurable number of active cores and supporting internal network
#38 | 2018-11-15Configuration of application software on multi-core image processor
#39 | 2018-11-15Program code transformations to improve image processor runtime efficiency
#40 | 2018-11-15Circuit to perform dual input value absolute value and sum operation
#41 | 2018-11-15Two dimensional masked shift instruction
#42 | 2018-08-16Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
#43 | 2018-01-04Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
#44 | 2018-01-04Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
#45 | 2018-01-04Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register
#46 | 2018-01-04Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
#47 | 2018-01-04Convolutional neural network on programmable two dimensional image processor
#48 | 2018-01-04Convolutional neural network on programmable two dimensional image processor
#49 | 2018-01-04Statistics operations on two dimensional image processor
#50 | 2018-01-04Statistics Operations On Two Dimensional Image Processor
#51 | 2017-10-26Two dimensional shift array for image processor
#52 | 2017-10-05Compiler managed memory for image processor
#53 | 2017-10-05Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
#54 | 2017-09-07Line buffer unit for image processor
#55 | 2017-09-07Sheet generator for image processor
#56 | 2017-09-07Macro I/O unit for image processor
#57 | 2017-09-07Architecture for high performance, power efficient, programmable image processing
#58 | 2017-08-31Macro I/O unit for image processor
#59 | 2017-08-31Compiler managed memory for image processor
#60 | 2017-08-31Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
#61 | 2017-08-31Energy efficient processor core architecture for image processor
#62 | 2017-08-24Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
#63 | 2017-08-24Multi-functional execution lane for image processor
#64 | 2017-08-24Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#65 | 2017-07-20Virtual linebuffers for image signal processors
#66 | 2017-06-08Multi-functional execution lane for image processor
#67 | 2016-10-27Line buffer unit for image processor
#68 | 2016-10-27Two dimensional shift array for image processor
#69 | 2016-10-27Sheet generator for image processor
#70 | 2016-10-27Architecture for high performance, power efficient, programmable image processing
#71 | 2016-10-27Energy efficient processor core architecture for image processor
#72 | 2016-10-27Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#73 | 2016-10-27Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
#74 | 2016-07-28Virtual linebuffers for image signal processors
#75 | 2015-01-22Variable fragment shading with surface recasting
#76 | 2014-08-14IMAGE PYRAMID PROCESSOR AND METHOD OF MULTI-RESOLUTION IMAGE PROCESSING
#77 | 2014-06-26Input output connector for accessing graphics fixed function units in a software-defined pipeline and a method of operating a pipeline
#78 | 2014-06-26METHOD AND MECHANISM FOR PREEMPTING CONTROL OF A GRAPHICS PIPELINE
#79 | 2014-06-26Graphics processing unit employing a standard processing unit and a method of constructing a graphics processing unit
#80 | 2014-06-26Tile shader for screen space, a method of rendering and a graphics processing unit employing the tile shader
#81 | 2014-06-19System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same
#82 | 2014-06-19SYSTEM AND METHOD FOR VERSIONING BUFFER STATES AND GRAPHICS PROCESSING UNIT INCORPORATING THE SAME
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