Inventor profile of:

Anirudh Devgan

City:

Austin, Texas

Country:

United States

Published Applications:

23

Last publication date:

2014-06-26

Top Assignees for applications by Anirudh Devgan

The entities that hold a legal rights for patent applications filed by inventor Devgan Anirudh:

Recent patent applications by Devgan Anirudh

Anirudh Devgan from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2014-06-26
US20140181762A1
Physics

Lithography aware leakage analysis

#2 | 2008-12-25
US20080319717A1
Physics

Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions

#3 | 2008-10-07
US11372557
-

Lithographically optimized placement tool

#4 | 2008-04-24
US20080094878A1
Physics

Ring oscillator row circuit for evaluating memory cell performance

#5 | 2008-02-28
US20080052653A1
Physics

Lithography aware timing analysis

#6 | 2008-02-28
US20080052646A1
Physics

Lithography aware leakage analysis

#7 | 2007-12-27
US20070300191A1
Physics

Efficient electromagnetic modeling of irregular metal planes

#8 | 2007-12-20
US20070291562A1
Physics

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

#9 | 2007-07-19
US20070165471A1
Physics

Internally asymmetric method for evaluating static memory cell dynamic stability

#10 | 2007-07-05
US20070153599A1
Physics

Method for evaluating leakage effects on static memory cell access time

#11 | 2007-04-19
US20070086232A1
Physics

Row circuit ring oscillator method for evaluating memory cell performance

#12 | 2007-03-15
US20070058466A1
Physics

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

#13 | 2007-03-15
US20070058448A1
Physics

Bitline variable methods and circuits for evaluating static memory cell dynamic stability

#14 | 2006-12-14
US20060282798A1
Physics

Efficient electromagnetic modeling of irregular metal planes

#15 | 2006-09-14
US20060203581A1
Physics

Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions

#16 | 2006-04-25
US9455057
-

Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes

#17 | 2006-02-14
US10448240
-

Method, apparatus, and program for block-based static timing analysis with uncertainty

#18 | 2005-11-22
US9668320
-

Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model

#19 | 2005-09-27
US10448241
-

Interconnect delay and slew metrics based on the lognormal distribution

#20 | 2005-06-23
US20050138584A1
Physics

Method, system, and product for verifying voltage drop across an entire integrated circuit package

#21 | 2005-03-15
US10306603
-

Method and system for extending delay and slew metrics to ramp inputs

#22 | 2005-02-24
US20050044515A1
Physics

Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit

#23 | 2005-01-11
US10646426
-

Method for determining the leakage power for an integrated circuit

InventorID:

818426 ⎘