Byron, Minnesota
United States
29
2023-03-02
The entities that hold a legal rights for patent applications filed by inventor Wait Charles D.:
Charles D. Wait from Byron, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Sleeping and waking-up address translation that conflicts with translation level of active page table walks
#2 | 2022-09-29Power optimized prefetching in set-associative translation lookaside buffer structure
#3 | 2022-09-15Unified translation miss queue for multiple address translation modes
#4 | 2022-02-17Determining page size via page table cache
#5 | 2020-03-05Promotion of ERAT cache entries
#6 | 2019-02-28Ensuring forward progress for nested translations in a memory management unit
#7 | 2019-02-28Ensuring forward progress for nested translations in a memory management unit
#8 | 2019-02-28Reducing translation latency within a memory management unit using external caching structures
#9 | 2019-02-28Reducing translation latency within a memory management unit using external caching structures
#10 | 2018-10-18MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
#11 | 2018-10-18MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
#12 | 2016-10-27Branch prediction with power usage prediction and control
#13 | 2015-12-24Branch prediction with power usage prediction and control
#14 | 2014-08-14Branch prediction with power usage prediction and control
#15 | 2013-07-25Dynamic range adjusting floating point execution unit
#16 | 2013-07-18Fault tolerant stability critical execution checking using redundant execution pipelines
#17 | 2013-06-20Instruction predication using instruction address pattern matching
#18 | 2013-05-30Processing core with speculative register preprocessing in unused execution unit cycles
#19 | 2013-05-02Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address
#20 | 2013-02-07Floating point execution unit with fixed point functionality
#21 | 2012-04-05Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits
#22 | 2011-12-29Programmable integrated processor blocks
#23 | 2011-12-08Fault tolerant stability critical execution checking using redundant execution pipelines
#24 | 2011-12-08Performing vector multiplication
#25 | 2010-05-20Pre-loading context states by inactive hardware thread in advance of context switch
#26 | 2010-02-18Redundant execution of instructions in multistage execution pipeline during unused execution cycles
#27 | 2010-02-18Data dependent instruction decode
#28 | 2010-01-28Dynamic range adjusting floating point execution unit
#29 | 2007-01-04Software debug support for cache flush with access to external data location(s) through debug port
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