Poughkeepsie, New York
United States
109
2021-06-24
The entities that hold a legal rights for patent applications filed by inventor Meaney Patrick J.:
Patrick J. Meaney from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#2 | 2020-04-16Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
#3 | 2020-03-26Common high and low random bit error correction logic
#4 | 2020-03-05Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
#5 | 2020-02-06Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#6 | 2019-10-17Common high and low random bit error correction logic
#7 | 2019-08-15Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#8 | 2019-08-08High efficiency redundant array of independent memory
#9 | 2019-07-25Register access in a distributed memory buffer system
#10 | 2019-06-20Error correction potency improvement via added burst beats in a dram access cycle
#11 | 2019-05-30High efficiency redundant array of independent memory
#12 | 2019-05-30Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
#13 | 2019-05-30Address/command chip controlled data chip address sequencing for a distributed memory buffer system
#14 | 2019-05-30Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
#15 | 2019-05-30Host controlled data chip address sequencing for a distributed memory buffer system
#16 | 2019-05-23Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
#17 | 2019-05-23Dynamically adjustable cyclic redundancy code rates
#18 | 2019-05-23Use of multiple cyclic redundancy codes for optimized fail isolation
#19 | 2019-05-23Dynamically adjustable cyclic redundancy code types
#20 | 2019-04-18Partial data replay in a distributed memory buffer system
#21 | 2019-03-14Memory mirror invocation upon detecting a correctable error
#22 | 2019-01-17Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
#23 | 2019-01-17Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
#24 | 2018-12-20Reduced latency error correction decoding
#25 | 2018-12-20Conditional memory spreading for heterogeneous memory sizes
#26 | 2018-11-15Reducing uncorrectable errors based on a history of correctable errors
#27 | 2018-09-18Partial data replay in a distributed memory buffer system
#28 | 2018-07-19Power-reduced redundant array of independent memory (RAIM) system
#29 | 2018-06-21Predictive scheduler for memory rank switching
#30 | 2018-06-21Predictive scheduler for memory rank switching
#31 | 2018-03-01Reducing uncorrectable errors based on a history of correctable errors
#32 | 2017-07-06Secure, targeted, customizable data removal
#33 | 2017-03-30Reducing uncorrectable errors based on a history of correctable errors
#34 | 2016-12-22Synchronization and order detection in a memory system
#35 | 2016-12-15Reestablishing synchronization in a memory system
#36 | 2016-12-08Dynamic cache row fail accumulation due to catastrophic failure
#37 | 2016-08-18Dynamic cache row fail accumulation due to catastrophic failure
#38 | 2016-08-18Dynamic cache row fail accumulation due to catastrophic failure
#39 | 2016-06-30Synchronization and order detection in a memory system
#40 | 2016-06-30Reestablishing synchronization in a memory system
#41 | 2016-06-16Combined rank and linear address incrementing utility for computer memory test operations
#42 | 2015-12-03Error injection and error counting during memory scrubbing operations
#43 | 2015-11-05Error injection and error counting during memory scrubbing operations
#44 | 2015-09-17Combined rank and linear address incrementing utility for computer memory test operations
#45 | 2015-01-15Early data delivery prior to error detection completion
#46 | 2015-01-15Stale data detection in marked channel for scrub
#47 | 2015-01-15Dual asynchronous and synchronous memory system
#48 | 2014-10-16Stale data detection in marked channel for scrub
#49 | 2014-09-18Replay suspension in a memory system
#50 | 2014-09-18Early data delivery prior to error detection completion
#51 | 2014-09-18Reestablishing synchronization in a memory system
#52 | 2014-09-18Dual asynchronous and synchronous memory system
#53 | 2014-09-18Synchronization and order detection in a memory system
#54 | 2014-09-18Address mapping including generic bits for universal addressing independent of memory type
#55 | 2014-09-18First-in-first-out queue-based command spreading
#56 | 2014-06-19System and method to inject a bit error on a bus lane
#57 | 2014-04-10Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems
#58 | 2014-04-10Per-rank channel marking in a memory system
#59 | 2013-12-19Bad wordline/array detection in memory
#60 | 2013-12-19Bad wordline/array detection in memory
#61 | 2013-12-19Bitline deletion
#62 | 2013-12-19Bitline deletion
#63 | 2013-12-19Bitline deletion
#64 | 2013-07-25Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems
#65 | 2013-07-25Hierarchical channel marking in a memory system
#66 | 2013-07-25PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM
#67 | 2013-07-25Heterogeneous recovery in a redundant memory system
#68 | 2013-07-25Homogeneous recovery in a redundant memory system
#69 | 2013-02-21Channel marking for chip mark overflow and calibration errors
#70 | 2013-02-07Collecting failure information on error correction code (ECC) protected data
#71 | 2012-08-02Correcting memory device and memory channel failures in the presence of known memory device failures
#72 | 2012-07-05Channel marking for chip mark overflow and calibration errors
#73 | 2011-12-29Failing bus lane detection using syndrome analysis
#74 | 2011-12-29High performance cache directory error correction code
#75 | 2011-12-29RAIM system using decoding of virtual ECC
#76 | 2011-12-29Error correction and detection in a redundant memory system
#77 | 2011-12-29Hierarchical error injection for complex RAIM/ECC design
#78 | 2011-12-29Homogeneous recovery in a redundant memory system
#79 | 2011-12-29Heterogeneous recovery in a redundant memory system
#80 | 2011-12-29User-controlled targeted cache purge
#81 | 2009-08-27Method, system and computer program product involving error thresholds
#82 | 2009-08-27Method, system and computer program product for processing error information in a system
#83 | 2009-06-25Collecting failure information on error correction code (ECC) protected data
#84 | 2009-04-23Method and apparatus for parallel and serial data transfer
#85 | 2009-03-12Multi nodal computer system and method for handling check stops in the multi nodal computer system
#86 | 2008-11-06Method for Stabilizing Asynchronous Interfaces
#87 | 2008-03-20Computer system apparatus for stabilizing asynchronous interfaces
#88 | 2007-12-27Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
#89 | 2007-12-27Late data launch for a double data rate elastic interface
#90 | 2007-12-27Double data rate chaining for synchronous DDR interfaces
#91 | 2007-12-27Method for resource sharing in a multiple pipeline environment
#92 | 2007-12-27Early directory access of a double data rate elastic interface
#93 | 2007-12-06Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code
#94 | 2007-12-06SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH ALL CHECKBITS TRANSFERRED LAST
#95 | 2007-12-06SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS DIAGNOSTIC FEATURES
#96 | 2007-12-06SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS TIMING IMPROVEMENTS
#97 | 2007-05-22Method for tagging uncorrectable errors for symmetric multiprocessors
#98 | 2007-02-08Method for enabling scan of defective ram prior to repair
#99 | 2006-10-26Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing
#100 | 2006-09-14Method for self-correcting cache using line delete, data logging, and fuse repair correction
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