Wappingers Falls, New York
United States
31
2021-04-08
The entities that hold a legal rights for patent applications filed by inventor Sinha Debjit:
Debjit Sinha from Wappingers Falls, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
#2 | 2020-11-10Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs
#3 | 2020-07-30Variable accuracy incremental timing analysis
#4 | 2019-09-19Parallel access to running electronic design automation (EDA) application
#5 | 2018-12-13PARALLEL ACCESS TO RUNNING EDA APPLICATION
#6 | 2018-12-13Parallel access to running electronic design automation (EDA) application
#7 | 2018-08-23Multi-sided variations for creating integrated circuits
#8 | 2018-08-23Multi-sided variations for creating integrated circuits
#9 | 2018-08-23Multi-sided variations for creating integrated circuits
#10 | 2018-03-15Accurate statistical timing for boundary gates of hierarchical timing models
#11 | 2018-02-15Incremental common path pessimism analysis
#12 | 2017-08-24Distributed timing analysis of a partitioned integrated circuit design
#13 | 2017-07-13Accurate statistical timing for boundary gates of hierarchical timing models
#14 | 2017-05-25Incremental common path pessimism analysis
#15 | 2017-05-11Variation-aware timing analysis using waveform construction
#16 | 2017-02-16Prioritized path tracing in statistical timing analysis of integrated circuits
#17 | 2017-01-19Statistical timing using macro-model considering statistical timing value entry
#18 | 2016-10-27Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints
#19 | 2016-01-14System and method for maintaining slack continuity in incremental statistical timing analysis
#20 | 2014-02-06Method for achieving an efficient statistical optimization of integrated circuits
#21 | 2013-11-19Device-based random variability modeling in timing analysis
#22 | 2013-06-20Performing statistical timing analysis with non-separable statistical and deterministic variations
#23 | 2013-06-06Statistical clock cycle computation
#24 | 2013-02-07Efficient slack projection for truncated distributions
#25 | 2012-05-10Performing statistical timing analysis with non-separable statistical and deterministic variations
#26 | 2010-10-21Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits
#27 | 2010-08-19Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits
#28 | 2010-07-15Method of performing timing analysis on integrated circuit chips with consideration of process variations
#29 | 2010-04-08Method and apparatus for efficient incremental statistical timing analysis and optimization
#30 | 2009-09-10Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis
#31 | 2009-03-19Method of constrained aggressor set selection for crosstalk induced noise
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