Inventor profile of:

Silke Penth

City:

Holzgerlingen

Country:

Germany

Published Applications:

15

Last publication date:

2026-06-18

Top Assignees for applications by Silke Penth

The entities that hold a legal rights for patent applications filed by inventor Penth Silke:

Recent patent applications by Penth Silke

Silke Penth from Holzgerlingen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-06-18
US20260169630A1
Physics

PERFORMING A READ OPERATION AND A CLEAR OPERATION IN A LATE SELECT ARRAY IN THE SAME CLOCK CYCLE

#2 | 2026-06-02
US18981959
Physics

Performing a read operation and a clear operation in a late select array in the same clock cycle

#3 | 2025-04-10
US20250118360A1
Physics

MEMORY DEVICE, ASSIST CELL AND DOUBLE ASSIST CELL FOR A MEMORY DEVICE

#4 | 2018-11-08
US20180322236A1
Physics

Field-effect transistor placement optimization for improved leaf cell routability

#5 | 2018-11-08
US20180322235A1
Physics

Field-effect transistor placement optimization for improved leaf cell routability

#6 | 2018-01-04
US20180005674A1
Physics

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

#7 | 2017-10-17
US15180114
Physics

Managing semiconductor memory array leakage current

#8 | 2017-09-12
US15258056
Physics

Managing semiconductor memory array leakage current

#9 | 2017-08-24
US20170243619A1
Physics

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

#10 | 2017-08-10
US20170228489A1
Physics

Layout of interconnect lines in integrated circuits

#11 | 2017-08-10
US20170228487A1
Physics

Layout of interconnect lines in integrated circuits

#12 | 2017-07-18
US15182178
Physics

Memory circuit

#13 | 2016-03-24
US20160086659A1
Physics

SRAM array comprising multiple cell cores

#14 | 2014-09-11
US20140254290A1
Physics

Local evaluation circuit for static random-access memory

#15 | 2014-07-10
US20140192602A1
Physics

Defective memory column replacement with load isolation

InventorID:

830946 ⎘