Sujat Jamil

Apparatus and method for avoiding conflicting entries in a storage structure

Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache

Method and apparatus for use of a preload instruction to improve efficiency of cache

Managing aliasing in a virtually indexed physically tagged cache

Interconnected ring network in a multi-processor system

Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture

Method and apparatus for processing speculative, out-of-order memory access instructions

Thread-aware cache memory management

Systems and methods for reducing interrupt latency

Method and apparatus for associating requests and responses with identification information

Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses

Detecting and reissuing of loop instructions in reorder structure

Cache memory bank selection

Method and apparatus for improving cache efficiency

Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison

Dynamic pipeline reconfiguration including changing a number of stages

Interconnected ring network in a multi-processor system

INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM

Programmable cache access protocol to optimize power consumption and performance

Method and apparatus for associating requests and responses with identification information

Programmable cache access protocol to optimize power consumption and performance

Method and apparatus for data-less bus query

Method and apparatus for hardware-configurable multi-policy coherence protocol

Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode