Inventor profile of:

Danilo Caraccio

City:

Buonalbergo

Country:

Italy

Published Applications:

50

Last publication date:

2025-10-16

Top Assignees for applications by Danilo Caraccio

The entities that hold a legal rights for patent applications filed by inventor Caraccio Danilo:

Recent patent applications by Caraccio Danilo

Danilo Caraccio from Buonalbergo, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-16
US20250321697A1
Physics

COMMAND QUEUING

#2 | 2024-09-19
US20240311012A1
Physics

HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE, AND ASSOCIATED MEMORY DEVICES, SYSTEMS, AND METHODS

#3 | 2024-08-01
US20240256186A1
Physics

COMMAND QUEUING

#4 | 2024-02-01
US20240037045A1
Physics

APPARATUSES AND METHODS FOR SECURING AN ACCESS PROTECTION SCHEME

#5 | 2023-05-18
US20230153204A1
Physics

Maintenance command interfaces for a memory system

#6 | 2023-02-23
US20230054662A1
Physics

Command queuing

#7 | 2022-06-23
US20220197504A1
Physics

Memory devices and systems for host controlled enablement of automatic background operations in a memory device

#8 | 2022-04-07
US20220107735A1
Physics

Memory operations on data

#9 | 2021-09-16
US20210286737A1
Physics

Apparatuses and methods for securing an access protection scheme

#10 | 2021-07-08
US20210208988A1
Physics

Memory management

#11 | 2021-07-01
US20210200478A1
Physics

Command queuing

#12 | 2020-12-10
US20200389778A1
Electricity

Wireless memory interface

#13 | 2020-07-23
US20200233585A1
Physics

DATA RELOCATION IN HYBRID MEMORY

#14 | 2020-05-14
US20200152267A1
Physics

Data state synchronization

#15 | 2019-12-19
US20190384700A1
Physics

Methods and apparatuses for requesting ready status information from a memory

#16 | 2019-12-05
US20190369878A1
Physics

Memory operations on data

#17 | 2019-07-18
US20190220192A1
Physics

Host controlled enablement of automatic background operations in a memory device

#18 | 2019-04-11
US20190108108A1
Physics

Memory management

#19 | 2019-04-04
US20190102112A1
Physics

Command queuing

#20 | 2019-01-31
US20190035461A1
Physics

Data state synchronization

#21 | 2019-01-17
US20190018618A1
Physics

Methods and apparatuses for executing a plurality of queued tasks in a memory

#22 | 2018-09-25
US15664014
Physics

Data state synchronization

#23 | 2018-05-10
US20180129575A1
Physics

Memory management

#24 | 2018-05-10
US20180129442A1
Physics

Systems and methods for providing file information in a memory system protocol

#25 | 2018-05-10
US20180129424A1
Physics

Data relocation in hybrid memory

#26 | 2018-05-10
US20180129423A1
Physics

Memory operations on data

#27 | 2018-02-08
US20180039572A1
Physics

Methods and apparatuses for requesting ready status information from a memory

#28 | 2017-12-07
US20170351458A1
Physics

Multi-partitioning of memories

#29 | 2017-11-02
US20170315734A1
Physics

Memory devices for detecting known initial states and related methods and electronic systems

#30 | 2017-06-08
US20170160973A1
Physics

Controller to manage NAND memories

#31 | 2017-03-23
US20170083260A1
Physics

Systems and methods for providing file information in a memory system protocol

#32 | 2016-12-15
US20160364179A1
Physics

Command queuing

#33 | 2016-08-11
US20160231932A1
Physics

Host controlled enablement of automatic background operations in a memory device

#34 | 2016-05-19
US20160140049A1
Physics

Wireless memory interface

#35 | 2016-04-07
US20160098223A1
Physics

Controller to manage NAND memories

#36 | 2016-03-24
US20160085476A1
Physics

Multi-partitioning of memories

#37 | 2015-10-08
US20150286585A1
Physics

Apparatuses and methods for securing an access protection scheme

#38 | 2015-07-30
US20150212738A1
Physics

Methods and apparatuses for executing a plurality of queued tasks in a memory

#39 | 2015-04-09
US20150100744A1
Physics

Methods and apparatuses for requesting ready status information from a memory

#40 | 2014-11-27
US20140351675A1
Physics

Controller to manage NAND memories

#41 | 2014-08-07
US20140223087A1
Physics

Multi-partitioning of memories

#42 | 2014-07-17
US20140201473A1
Physics

Host controlled enablement of automatic background operations in a memory device

#43 | 2013-12-12
US20130332800A1
Physics

Secondary memory to store error correction information

#44 | 2013-10-10
US20130268825A1
Physics

Secondary memory to store a varying amount of overhead information

#45 | 2013-06-04
US12346015
-

Secondary memory element for non-volatile memory

#46 | 2013-01-17
US20130019058A1
Physics

Multi-partitioning of memories

#47 | 2012-11-06
US12628152
-

Multi-partitioning feature on e-MMC

#48 | 2012-07-26
US20120191924A1
Physics

Preparation of memory device for access using memory access type indicator signal

#49 | 2012-07-12
US20120179860A1
Physics

SUSPENSION OF MEMORY OPERATIONS FOR REDUCED READ LATENCY IN MEMORY ARRAYS

#50 | 2011-12-15
US20110307762A1
Physics

Controller to execute error correcting code algorithms and manage NAND memories

InventorID:

841478 ⎘