Inventor profile of:

Emanuele Confalonieri

City:

Lesmo

Country:

Italy

Published Applications:

45

Last publication date:

2025-10-23

Top Assignees for applications by Emanuele Confalonieri

The entities that hold a legal rights for patent applications filed by inventor Confalonieri Emanuele:

Recent patent applications by Confalonieri Emanuele

Emanuele Confalonieri from Lesmo, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-23
US20250328247A1
Physics

FULL DUPLEX MEMORY SYSTEM

#2 | 2022-04-07
US20220107735A1
Physics

Memory operations on data

#3 | 2021-07-08
US20210208988A1
Physics

Memory management

#4 | 2021-06-03
US20210166775A1
Physics

Data state synchronization

#5 | 2021-03-04
US20210064261A1
Physics

Multi-partitioning of memories

#6 | 2020-12-31
US20200409607A1
Physics

HYBRID MEMORY SYSTEM

#7 | 2020-09-24
US20200301841A1
Physics

Latency-based storage in a hybrid memory system

#8 | 2020-09-17
US20200293211A1
Physics

Latency-based storage in a hybrid memory system

#9 | 2020-07-23
US20200233585A1
Physics

DATA RELOCATION IN HYBRID MEMORY

#10 | 2020-05-14
US20200152267A1
Physics

Data state synchronization

#11 | 2020-04-02
US20200104268A1
Physics

Interface for memory having a cache and multiple independent arrays

#12 | 2020-03-12
US20200082900A1
Physics

Data state synchronization involving memory cells having an inverted data state written thereto

#13 | 2019-12-05
US20190369878A1
Physics

Memory operations on data

#14 | 2019-09-26
US20190294547A1
Physics

Latency-based storage in a hybrid memory system

#15 | 2019-09-26
US20190294363A1
Physics

Latency-based storage in a hybrid memory system

#16 | 2019-09-26
US20190294356A1
Physics

Latency-based storage in a hybrid memory system

#17 | 2019-09-19
US20190286586A1
Physics

Interface for memory having a cache and multiple independent arrays

#18 | 2019-09-12
US20190279689A1
Physics

Temperature-based memory operations

#19 | 2019-07-04
US20190206452A1
Physics

Temperature-based memory operations

#20 | 2019-06-06
US20190171385A1
Physics

Multi-partitioning of memories

#21 | 2019-04-11
US20190108108A1
Physics

Memory management

#22 | 2019-01-31
US20190035461A1
Physics

Data state synchronization

#23 | 2018-09-25
US15664014
Physics

Data state synchronization

#24 | 2018-06-07
US20180158527A1
Physics

VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS

#25 | 2018-05-10
US20180129575A1
Physics

Memory management

#26 | 2018-05-10
US20180129442A1
Physics

Systems and methods for providing file information in a memory system protocol

#27 | 2018-05-10
US20180129424A1
Physics

Data relocation in hybrid memory

#28 | 2018-05-10
US20180129423A1
Physics

Memory operations on data

#29 | 2017-12-07
US20170351458A1
Physics

Multi-partitioning of memories

#30 | 2017-03-23
US20170083260A1
Physics

Systems and methods for providing file information in a memory system protocol

#31 | 2016-03-24
US20160085476A1
Physics

Multi-partitioning of memories

#32 | 2016-02-25
US20160055103A1
Physics

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

#33 | 2015-04-02
US20150095551A1
Physics

VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS

#34 | 2015-01-29
US20150032927A1
Physics

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

#35 | 2014-08-07
US20140223087A1
Physics

Multi-partitioning of memories

#36 | 2014-05-29
US20140149823A1
Physics

Memory with guard value dependent error correction

#37 | 2013-03-05
US12628166
-

Dynamic range unlock or lock memory device and method to operate the same

#38 | 2013-01-17
US20130019058A1
Physics

Multi-partitioning of memories

#39 | 2012-11-06
US12628152
-

Multi-partitioning feature on e-MMC

#40 | 2012-09-06
US20120226880A1
Physics

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

#41 | 2012-07-26
US20120191924A1
Physics

Preparation of memory device for access using memory access type indicator signal

#42 | 2010-08-12
US20100202194A1
Physics

Dynamically allocable regions in non-volatile memories

#43 | 2010-06-24
US20100157718A1
Physics

Configurable latching for asynchronous memories

#44 | 2008-09-04
US20080212369A1
Physics

Method of managing a memory device employing three-level cells

#45 | 2007-05-10
US20070103973A1
Physics

Memory architecture

InventorID:

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