Paderborn
Germany
34
2026-03-26
The entities that hold a legal rights for patent applications filed by inventor KALTE Heiko:
Heiko KALTE from Paderborn, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD FOR CARRYING OUT AN OPTIMIZATION OF AT LEAST ONE SPECIFIC SIGNAL PATH OF A CIRCUIT DESIGN TO BE MAPPED IN AN FPGA, AND SOFTWARE FOR GENERATING A CIRCUIT DESIGN TO BE MAPPED IN AN FPGA
#2 | 2025-08-14PROGRAMMABLE GATE ARRAY AND METHOD OF GENERATING CONFIGURATION DATA FOR PROGRAMMING A GATE ARRAY
#3 | 2025-01-16METHOD FOR FPGA BUILD AND INITIALIZATION
#4 | 2024-08-08METHOD AND SYSTEM FOR TRANSFORMING RECORDED COMMUNICATION DATA
#5 | 2024-01-25METHOD AND DEVICE FOR DETECTING ERRORS IN ROUTES AND CALCULATIONS WITHIN AN FPGA
#6 | 2023-12-28Method for effectively increasing a memory on an FPGA
#7 | 2023-12-28Method for programming an FPGA
#8 | 2023-10-19METHOD FOR DOCUMENTING COMPUTING STEPS OF A REAL TIME SYSTEM EXECUTED ON A COMPUTER CORE OF A PROCESSOR, PROCESSOR AND REAL TIME SYSTEM
#9 | 2023-06-22METHOD FOR CHANGING A BITWIDTH OF AN FPGA CONFIGURATION
#10 | 2023-06-22Method for data communication between subregions of an FPGA
#11 | 2023-06-22Computer-implemented method for creating a hierarchical block diagram
#12 | 2023-03-16METHOD OF ADDING ANOTHER CIRCUIT COMPONENT
#13 | 2022-11-10METHOD FOR PROGRAMMING AN FPGA
#14 | 2022-02-24Computer-implemented method for restructuring a predefined distributed real-time simulation network
#15 | 2021-09-30Method for programming a programmable gate array in a distributed computer system
#16 | 2021-08-19Method, computer-based system and computer program product for planning partitions for a programmable gate array
#17 | 2020-11-19Method for troubleshooting the program logic of a system of distributed progammable gate arrays
#18 | 2020-05-07COMPUTER NETWORK WITH A FIRST AND A SECOND SYNCHRONIZING SIGNAL TRANSMITTER
#19 | 2020-04-30Procedure for reviewing an FPGA-program
#20 | 2019-07-11Incremental generation of an FPGA implementation with a graph-based similarity search
#21 | 2019-05-30Method for operating a real -time-capable simulation network having multiple network nodes for computing a simulation model, also computer program product relating thereto, and computer-readable storage medium
#22 | 2019-05-16Method for producing an association list
#23 | 2019-05-09METHOD FOR READING OUT VARIABLES FROM AN FPGA
#24 | 2018-11-08Method for detecting the topology of electrical wiring
#25 | 2017-11-16Method for creating an FPGA netlist
#26 | 2017-11-16METHOD FOR TEMPORALLY SYNCHRONIZING THE OUTPUT AND/OR TEMPORALLY SYNCHRONIZING THE PROCESSING OF SIGNALS
#27 | 2017-05-04Method and device for accelerated access to signals of a programmable logic device
#28 | 2017-04-27Method for determining the power consumption of a programmable logic device
#29 | 2016-06-09Random access to signal values of an FPGA at runtime
#30 | 2016-03-24Determination of signals for readback from FPGA
#31 | 2015-12-31Implementing a constant in FPGA code
#32 | 2015-12-03Alteration of a signal value for an FPGA at runtime
#33 | 2015-11-19Method for automatically generating a netlist of an FPGA program
#34 | 2014-08-14Random access to signal values of an FPGA at runtime
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