Howard C. Kirsch

Double gated 4F2 dram CHC cell and methods of fabricating the same

Apparatuses and methods for reducing current leakage in a memory

Apparatuses and methods for adjusting deactivation voltages

Memory device word line drivers and methods

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers

Line driver circuits, methods, and apparatuses

Double gated 4F2 dram CHC cell and methods of fabricating the same

Double gated 4F2 dram CHC cell and methods of fabricating the same

Memory device word line drivers and methods

MEMORY DEVICE WORD LINE DRIVERS AND METHODS

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers

Memory structure having volatile and non-volatile memory portions

Devices and methods for a threshold voltage difference compensated sense amplifier

Memory structure having volatile and non-volatile memory portions

Devices and methods for a threshold voltage difference compensated sense amplifier

Multiple-depth STI trenches in integrated circuit fabrication

Open digit line array architecture for a memory array

Level shifter for low voltage operation

Trench buried bit line memory devices and methods thereof

Memory devices having reduced coupling noise between wordlines

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Methods of reducing coupling noise between wordlines

Open digit line array architecture for a memory array

Voltage level shifting circuit and method

Memory devices having reduced coupling noise between wordlines

Level shifter for low voltage operation

Multiple-depth STI trenches in integrated circuit fabrication

Voltage level shifting circuit and method

Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

Method and system for accelerating coupling of digital signals

Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line

Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage

Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage

Trench buried bit line memory devices and methods thereof

System and method to avoid voltage read errors in open digit line array dynamic random access memories