Christopher Edward Koob

Reducing metadata size in compressed memory systems of processor-based systems

Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems

Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur

REDUCING OR AVOIDING BUFFERING OF EVICTED CACHE DATA FROM AN UNCOMPRESSED CACHE MEMORY IN A COMPRESSED MEMORY SYSTEM TO AVOID STALLING WRITE OPERATIONS

Priority-based storage and access of compressed memory lines in memory in a processor-based system

Bandwidth/resource management for multithreaded processors

Selective translation lookaside buffer search and page fault

Adaptive mode translation lookaside buffer search and access fault

Independent power collapse methodology

Coprocessor for out-of-order loads

Systems and methods of executing multiple hypervisors using multiple sets of processors

Externally programmable memory management unit

Configurable cache and method to configure same

Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors

Write-only dataless state for maintaining cache coherency

Hybrid write-through/write-back cache policy managers, and related systems and methods

Computer system with processor local coherency for virtualized input/output

Data storage for voltage domain crossings

Configurable cache and method to configure same

System and method to access a portion of a level two memory and a level one memory

Dedicated Arithmetic Decoding Instruction

Configurable cache and method to configure same

Memory management unit directed access to system interfaces

Selective preclusion of a bus access request

Power-efficient sign extension for booth multiplication methods and systems

Booth multiplier with enhanced reduction tree circuitry

System and method of counting leading zeros and counting leading ones in a digital signal processor

System and method of performing two's complement operations in a digital signal processor