Mississauga
Canada
25
2021-07-15
The entities that hold a legal rights for patent applications filed by inventor Bourgeault Mark:
Mark Bourgeault from Mississauga, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
Methods for optimizing circuit performance via configurable clock skews
#2 | 2020-04-23Method and apparatus for performing incremental compilation using structural netlist comparison
#3 | 2020-02-06Methods for optimizing circuit performance via configurable clock skews
#4 | 2019-12-26Integrated circuit applications using partial reconfiguration
#5 | 2019-08-15Method and apparatus for performing incremental compilation using structural netlist comparison
#6 | 2019-08-06Integrated circuit applications using partial reconfiguration
#7 | 2019-04-30Method and apparatus for performing incremental compilation using structural netlist comparison
#8 | 2019-02-28METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK SKEWS
#9 | 2019-01-08Techniques for adjusting latency of a clock signal to affect supply voltage
#10 | 2018-07-31Methods for optimizing circuit performance via configurable clock skews
#11 | 2017-03-21Methods for optimizing circuit performance via configurable clock skews
#12 | 2017-02-28Integrated circuit applications using partial reconfiguration
#13 | 2016-09-15Method and apparatus for placing and routing partial reconfiguration modules
#14 | 2015-11-10Automatic asynchronous signal pipelining
#15 | 2014-09-09Automatic asynchronous signal pipelining
#16 | 2014-08-21Method and apparatus for placing and routing partial reconfiguration modules
#17 | 2013-09-17Automatic asynchronous signal pipelining
#18 | 2013-08-06Method and apparatus for performing automated timing closure analysis for systems implemented on target devices
#19 | 2012-09-06Method and apparatus for placement and routing of partial reconfiguration modules
#20 | 2012-05-29Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
#21 | 2011-06-09Preventing information leakage between components on a programmable chip in the presence of faults
#22 | 2010-03-09Automatic asynchronous signal pipelining
#23 | 2008-08-19Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
#24 | 2008-08-12Method and apparatus for performing integrated global routing and buffer insertion
#25 | 2005-11-29Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
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