Inventor profile of:

Anton P. Eppich

City:

Boise, Idaho

Country:

United States

Published Applications:

18

Last publication date:

2023-12-07

Top Assignees for applications by Anton P. Eppich

The entities that hold a legal rights for patent applications filed by inventor Eppich Anton P.:

Recent patent applications by Eppich Anton P.

Anton P. Eppich from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-12-07
US20230395529A1
Electricity

PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH THREE STRIPE TECHNIQUE

#2 | 2023-12-07
US20230395528A1
Electricity

PATTERNING OF 3D NAND PILLARS AND FLYING BUTTRESS SUPPORTS WITH TWO STRIPE TECHNIQUE

#3 | 2023-06-08
US20230180467A1
Electricity

Vertical access line in a folded digitline sense amplifier

#4 | 2022-03-01
US17090764
Electricity

Integrated assemblies

#5 | 2014-09-04
US20140248554A1
Physics

Sub-resolution assist devices and methods

#6 | 2014-08-28
US20140241025A1
Physics

DRAM cell design with folded digitline sense amplifier

#7 | 2011-09-29
US20110235009A1
Physics

Sub-resolution assist devices and methods

#8 | 2011-06-30
US20110156116A1
Electricity

Relaxed-pitch method of aligning active area to digit line

#9 | 2011-02-24
US20110042734A1
Electricity

Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same

#10 | 2009-08-27
US20090215236A1
Electricity

Relaxed-pitch method of aligning active area to digit line

#11 | 2008-11-13
US20080278700A1
Physics

Sub-resolution assist devices and methods

#12 | 2008-06-12
US20080137392A1
Physics

Dram cell design with folded digitline architecture and angled active areas

#13 | 2008-01-24
US20080017905A1
Electricity

Memory cell with buried digit line

#14 | 2007-09-20
US20070217245A1
Physics

6FDRAM cell design with 3F-pitch folded digitline sense amplifier

#15 | 2007-06-28
US20070145450A1
Physics

DRAM cell design with folded digitline sense amplifier

#16 | 2006-12-14
US20060278911A1
Electricity

Relaxed-pitch method of aligning active area to digit line

#17 | 2006-03-02
US20060043473A1
Electricity

Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same

#18 | 2006-03-02
US20060043431A1
Electricity

Memory array with overlapping buried digit line and active area and method for forming same

InventorID:

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