Fremont, California
United States
33
2021-06-03
The entities that hold a legal rights for patent applications filed by inventor Jackson Bryan L.:
Bryan L. Jackson from Fremont, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
#2 | 2019-12-05Yield tolerance in a neurosynaptic system
#3 | 2019-09-26Peripheral device interconnections for neurosynaptic systems
#4 | 2018-10-04Yield tolerance in a neurosynaptic system
#5 | 2018-08-16Dual deterministic and stochastic neurosynaptic core circuit
#6 | 2018-07-05Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
#7 | 2018-04-12Scaling multi-core neurosynaptic networks across chip boundaries
#8 | 2018-03-22Converting spike event data to digital numeric data
#9 | 2018-03-22Converting digital numeric data to spike event data
#10 | 2017-10-05Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency
#11 | 2017-07-13Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs
#12 | 2017-06-01Streaming programmable point mapper and compute hardware
#13 | 2017-05-04Array of processor core circuits with reversible tiers
#14 | 2017-03-09Dual deterministic and stochastic neurosynaptic core circuit
#15 | 2016-12-08Implementing stochastic networks using magnetic tunnel junctions
#16 | 2016-11-03Yield tolerance in a neurosynaptic system
#17 | 2016-11-03Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
#18 | 2016-11-03Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits
#19 | 2016-09-15Coupling parallel event-driven computation with serial computation
#20 | 2016-09-15COUPLING PARALLEL EVENT-DRIVEN COMPUTATION WITH SERIAL COMPUTATION
#21 | 2016-08-11Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
#22 | 2016-08-04Scaling multi-core neurosynaptic networks across chip boundaries
#23 | 2016-05-26Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
#24 | 2016-03-24Self-timed, event-driven neurosynaptic core controller
#25 | 2016-03-24Converting spike event data to digital numeric data
#26 | 2016-03-24Converting digital numeric data to spike event data
#27 | 2016-02-25Peripheral device interconnections for neurosynaptic systems
#28 | 2015-11-12Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
#29 | 2015-10-01Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs
#30 | 2015-09-17Implementing stochastic networks using magnetic tunnel junctions
#31 | 2015-04-23Coupling parallel event-driven computation with serial computation
#32 | 2015-02-05Dual deterministic and stochastic neurosynaptic core circuit
#33 | 2014-08-28Array of processor core circuits with reversible tiers
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