Jun Sawada

MECHANISM FOR EFFICIENT MASSIVELY-CONCURRENT CONDITIONAL COMPUTATION

Runtime reconfigurable neural network processor core

AN EFFICIENT METHOD FOR VLSI IMPLEMENTATION OF USEFUL NEURAL NETWORK ACTIVATION FUNCTIONS

MODULAR NEURAL NETWORK COMPUTING APPARATUS WITH DISTRIBUTED NEURAL NETWORK STORAGE

NEURAL NETWORK ACCELERATOR OUTPUT RANKING

HORIZONTAL AND VERTICAL ASSERTIONS FOR VALIDATION OF NEUROMORPHIC HARDWARE

SYMBOLIC VALIDATION OF NEUROMORPHIC HARDWARE

CONFLICT-FREE, STALL-FREE, BROADCAST NETWORK ON CHIP

CHIPS SUPPORTING CONSTANT TIME PROGRAM CONTROL OF NESTED LOOPS

MEMORY-MAPPED NEURAL NETWORK ACCELERATOR FOR DEPLOYABLE INFERENCE SYSTEMS

Neural network weight distribution from a grid of memory elements

COMPRESSED WEIGHT DISTRIBUTION IN NETWORKS OF NEURAL PROCESSORS

Flexible precision neural inference processing unit

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

3D NEURAL INFERENCE PROCESSING UNIT ARCHITECTURES

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Performing error detection during deterministic program execution

Massively parallel neural inference computing elements

Compound instruction set architecture for a neural inference chip

Networks for distributing parameters and data to neural network compute cores

Data representation for dynamic precision in neural network cores

MULTI-AGENT INSTRUCTION EXECUTION ENGINE FOR NEURAL INFERENCE PROCESSING

Selective multicast delivery on a bus-based interconnect

Data distribution in an array of neural network cores

SCHEDULER FOR MAPPING NEURAL NETWORKS ONTO AN ARRAY OF NEURAL CORES IN AN INFERENCE PROCESSING UNIT

HIERARCHICAL PARALLELISM IN A NETWORK OF DISTRIBUTED NEURAL NETWORK CORES

Instruction distribution in an array of neural network cores

Memory-mapped interface to message-passing computing systems

Runtime reconfigurable neural network processor core

Parallel computational architecture with reconfigurable core-level and vector-level parallelism

Yield tolerance in a neurosynaptic system

CENTRAL SCHEDULER AND INSTRUCTION DISPATCHER FOR A NEURAL INFERENCE PROCESSOR

TIME, SPACE, AND ENERGY EFFICIENT NEURAL INFERENCE VIA PARALLELISM AND ON-CHIP MEMORY

Massively parallel neural inference computing elements

Defect resistant designs for location-sensitive neural network processor arrays

BLOCK TRANSFER OF NEURON OUTPUT VALUES THROUGH DATA MEMORY FOR NEUROSYNAPTIC PROCESSORS

Peripheral device interconnections for neurosynaptic systems

Memory-mapped interface for message passing computing systems

Yield tolerance in a neurosynaptic system

Dual deterministic and stochastic neurosynaptic core circuit

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

Scaling multi-core neurosynaptic networks across chip boundaries

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency

Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs

Node isolation for protection from electrostatic discharge (ESD) damage

Array of processor core circuits with reversible tiers

Dual deterministic and stochastic neurosynaptic core circuit

Yield tolerance in a neurosynaptic system

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Scaling multi-core neurosynaptic networks across chip boundaries

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

Self-timed, event-driven neurosynaptic core controller

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Peripheral device interconnections for neurosynaptic systems

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damage

Dual deterministic and stochastic neurosynaptic core circuit

Array of processor core circuits with reversible tiers

Model checking in state transition machine verification

Verifying data intensive state transition machines related application

Verifying the error bound of numerical computation implemented in computer systems

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Method and system for a wiring-efficient permute unit

Scanning Latches Using Selecting Array

Scanning Latches Using Selecting Array

Fused booth encoder multiplexer

Fused booth encoder multiplexer

Scanning latches using selecting array

Replaceable sequenced one-time pads for detection of cloned service client

Fused booth encoder multiplexer