Schenectady, New York
United States
153
2020-03-12
The entities that hold a legal rights for patent applications filed by inventor He Hong:
Hong He from Schenectady, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Silicon germanium alloy fins with reduced defects
#2 | 2020-03-05Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#3 | 2019-12-12Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#4 | 2019-12-12Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#5 | 2019-06-06Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning
#6 | 2019-01-17Fin formation in fin field effect transistors
#7 | 2019-01-03Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning
#8 | 2018-11-15Self-aligned contact process enabled by low temperature
#9 | 2018-11-08Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
#10 | 2018-11-01Method of forming silicon germanium and silicon fins on oxide from bulk wafer
#11 | 2018-10-18Silicon germanium fin channel formation
#12 | 2018-08-09Critical dimension shrink through selective metal growth on metal hardmask sidewalls
#13 | 2018-04-05FinFET device with abrupt junctions
#14 | 2018-04-05Fabrication of silicon germanium-on-insulator FinFET
#15 | 2018-03-15Method and structure for forming a dense array of single crystalline semiconductor nanocrystals
#16 | 2018-03-08Preventing strained fin relaxation
#17 | 2018-03-01Structure and process to tuck fin tips self-aligned to gates
#18 | 2018-03-01Structure and process to tuck fin tips self-aligned to gates
#19 | 2017-12-21Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
#20 | 2017-10-12Directional deposition of protection layer
#21 | 2017-09-21Fin density control of multigate devices through sidewall image transfer processes
#22 | 2017-09-07Directional deposition of protection layer
#23 | 2017-07-06Silicon germanium fin channel formation
#24 | 2017-07-06Fin formation in fin field effect transistors
#25 | 2017-07-06LOW TEMPERATURE SELECTIVE DEPOSITION EMPLOYING A GERMANIUM-CONTAINING GAS ASSISTED ETCH
#26 | 2017-06-15Silicon germanium alloy fins with reduced defects
#27 | 2017-06-15Silicon germanium alloy fins with reduced defects
#28 | 2017-06-15Middle of the line integrated efuse in trench EPI structure
#29 | 2017-06-15Middle of the line integrated eFuse in trench EPI structure
#30 | 2017-05-25Critical dimension shrink through selective metal growth on metal hardmask sidewalls
#31 | 2017-05-18Self-aligned contact process enabled by low temperature
#32 | 2017-05-02FinFET device with channel strain
#33 | 2017-04-27Preventing strained fin relaxation
#34 | 2017-04-06Hybrid substrate engineering in CMOS finFET integration for mobility improvement
#35 | 2017-03-30Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity
#36 | 2017-03-30Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#37 | 2017-03-30Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#38 | 2017-03-16Fin isolation on a bulk wafer
#39 | 2017-03-09Formation of SiGe nanotubes
#40 | 2017-02-23Strained finFET device fabrication
#41 | 2017-02-23Strained finFET device fabrication
#42 | 2017-02-23Strained FinFET device fabrication
#43 | 2017-02-23Strained finFET device fabrication
#44 | 2017-02-16Hybrid substrate engineering in CMOS finFET integration for mobility improvement
#45 | 2017-02-16Silicon germanium fin channel formation
#46 | 2017-02-16Hybrid substrate engineering in CMOS finFET integration for mobility improvement
#47 | 2017-02-09LOW-K SPACER FOR RMG FINFET FORMATION
#48 | 2017-02-09Substrate with strained and relaxed silicon regions
#49 | 2017-02-02Semiconductor device including fin having condensed channel region
#50 | 2017-02-02SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION
#51 | 2017-02-02FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator
#52 | 2017-02-02Bulk fin formation with vertical fin sidewall profile
#53 | 2017-01-19Silicon germanium fin channel formation
#54 | 2017-01-19Silicon germanium and silicon fins on oxide from bulk wafer
#55 | 2016-12-29Fabrication of silicon germanium-on-insulator finFET
#56 | 2016-12-29Tone inverted directed self-assembly (DSA) fin patterning
#57 | 2016-12-06FinFET device with channel strain
#58 | 2016-12-01Preventing strained fin relaxation by sealing fin ends
#59 | 2016-12-01Critical dimension shrink through selective metal growth on metal hardmask sidewalls
#60 | 2016-12-01Critical dimension shrink through selective metal growth on metal hardmask sidewalls
#61 | 2016-11-24Structure and process to tuck fin tips self-aligned to gates
#62 | 2016-11-24Directly forming SiGe fins on oxide
#63 | 2016-11-22Strained finFET device fabrication
#64 | 2016-11-17Bulk fin formation with vertical fin sidewall profile
#65 | 2016-11-17Method and structure for forming a dense array of single crystalline semiconductor nanocrystals
#66 | 2016-11-15Channel protection during fin fabrication
#67 | 2016-11-10Work function metal fill for replacement gate fin field effect transistor process
#68 | 2016-11-03Silicon germanium alloy fins with reduced defects
#69 | 2016-10-27Method and structure of forming FinFET electrical fuse structure
#70 | 2016-10-27Method and structure of forming FinFET electrical fuse structure
#71 | 2016-10-18CMOS structures with selective tensile strained NFET fins and relaxed PFET fins
#72 | 2016-10-13Work function metal fill for replacement gate fin field effect transistor process
#73 | 2016-10-06Hybrid aspect ratio trapping
#74 | 2016-08-30Directly forming SiGe fins on oxide
#75 | 2016-08-25Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
#76 | 2016-08-25Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
#77 | 2016-08-16Silicon germanium and silicon fins on oxide from bulk wafer
#78 | 2016-08-11Dual isolation on SSOI wafer
#79 | 2016-08-11CMOS structure on SSOI wafer
#80 | 2016-08-11Dual isolation on SSOI wafer
#81 | 2016-08-11CMOS structure on SSOI wafer
#82 | 2016-08-04Replacement fin process in SSOI wafer
#83 | 2016-08-04Replacement fin process in SSOI wafer
#84 | 2016-07-28Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures
#85 | 2016-07-28Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
#86 | 2016-07-14Self-aligned contact process enabled by low temperature
#87 | 2016-07-14Bottom-up metal gate formation on replacement metal gate finFET devices
#88 | 2016-06-30Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions
#89 | 2016-06-30Silicon germanium-on-insulator FinFET
#90 | 2016-06-30Enriched, high mobility strained fin having bottom dielectric isolation
#91 | 2016-06-30Enriched, high mobility strained fin having bottom dielectric isolation
#92 | 2016-06-16FinFET with a silicon germanium alloy channel and method of fabrication thereof
#93 | 2016-06-14Tone inverted directed self-assembly (DSA) fin patterning
#94 | 2016-05-24CMOS structures with selective tensile strained NFET fins and relaxed PFET fins
#95 | 2016-05-12Microstructure of metal interconnect layer
#96 | 2016-05-03FinFET device with channel strain
#97 | 2016-04-28Gate structure integration scheme for fin field effect transistors
#98 | 2016-04-21Fin formation in fin field effect transistors
#99 | 2016-03-31EPITAXIALLY GROWN QUANTUM WELL FINFETS FOR ENHANCED PFET PERFORMANCE
#100 | 2016-03-31Epitaxially grown quantum well finFETs for enhanced pFET performance
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