Mark C. HAKEY

Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules

Structure having substantially parallel resistor material lengths

Field effect transistor

METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR

Shared gate for conventional planar device and horizontal CNT

Structure for heavy ion tolerant device, method of manufacturing the same and structure thereof

Chemical and particulate filters containing chemically modified carbon nanotube structures

Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity

Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer

Resistor and design structure having substantially parallel resistor material lengths

Resistor and design structure having resistor material length with sub-lithographic width

Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules

Field effect transistor

Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system

Carbon nanotube conductor for trench capacitors

CMOS gate structures fabricated by selective oxidation

Chemical and particulate filters containing chemically modified carbon nanotube structures

Exposures system including chemical and particulate filters containing chemically modified carbon nanotube structures

Chemical and particulate filters containing chemically modified carbon nanotube structures

Chemical and particulate filters containing chemically modified carbon nanotube structures

Carbon nanotubes as low voltage field emission sources for particle precipitators

METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE

Radiation hardened FinFET

Simultaneous conditioning of a plurality of memory cells through series resistors

Immersion lithography with equalized pressure on at least projection optics component and wafer

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

SEMICONDUCTOR DEVICES WITH BURIED ISOLATION REGIONS

Shallow trench isolation formation

ILLUMINATION LIGHT IN IMMERSION LITHOGRAPHY STEPPER FOR PARTICLE OR BUBBLE DETECTION

METHOD AND STRUCTURE FOR FORMING SELF-PLANARIZING WIRING LAYERS IN MULTILEVEL ELECTRONIC DEVICES

Simultaneous conditioning of a plurality of memory cells through series resistors

Method of doping a gate electrode of a field effect transistor

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

Wiring paterns formed by selective metal plating

Integrated carbon nanotube sensors

CMOS gate structures fabricated by selective oxidation

Implantation of gate regions in semiconductor device fabrication

Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography

Pattern density control using edge printing processes

Semiconductor transistors with contact holes close to gates

Shrinking contact apertures through LPD oxide

Accessible chip stack and process of manufacturing thereof

Sidewall image transfer (SIT) technologies

Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM

Carbon nanotubes as low voltage field emission sources for particle precipitators

Vertical dual gate field effect transistor

Non-volatile switching and memory devices using vertical nanotubes

FINFET GATE FORMED OF CARBON NANOTUBES

Shared gate for conventional planar device and horizontal CNT

Immersion lithography with equalized pressure on at least projection optics component and wafer

Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

Method of doping a gate electrode of a field effect transistor

Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom

Shallow trench isolation formation

Methods for metal plating of gate conductors and semiconductors formed thereby

Methods for providing gate conductors on semiconductors and semiconductors formed thereby

Canary device for failure analysis

Implantation of gate regions in semiconductor device fabrication

Double-gate FETs (Field Effect Transistors)

Semiconductor devices with buried isolation regions

Vertical carbon nanotube transistor integration

Process for oxide cap formation in semiconductor manufacturing

Shallow trench isolation formation

Wiring patterns formed by selective metal plating

Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions

Method and apparatus for immersion lithography

Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system

Low-k dielectric layer based upon carbon nanostructures

Reduced mask count gate conductor definition

Sub-lithographic imaging techniques and processes

Integrated carbon nanotube sensors

Wiring structure for integrated circuit with reduced intralevel capacitance

Irradiation assisted reactive ion etching

Method of fabricating shallow trench isolation by ultra-thin simox processing

Integrated semiconductor device having co-planar device surfaces

Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material

WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE

Method of fabricating shallow trench isolation by ultra-thin SIMOX processing

Semiconductor with contact contacting diffusion adjacent gate electrode

Increased capacitance trench capacitor

Methods using disposable and permanent films for diffusion and implantation doping

Liquid-filled balloons for immersion lithography

Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions

Vertical Carbon Nanotube Field Effect Transistor

Alternating phase mask built by additive film deposition

Dual gate logic device

Patterned SOI by oxygen implantation and annealing

Method of forming gas dielectric with support structure

Method for etching a semiconductor substrate using germanium hard mask

Patterned SOI by oxygen implantation and annealing