Rode R. Mora

SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Split gate non-volatile memory cell

Semiconductor fabrication process including silicide stringer removal processing

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Split gate memory cell method

Semiconductor structure pattern formation

Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer

Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same

Method for forming a stressor structure

Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration

Method of forming a semiconductor isolation trench

Method of making an inverted-T channel transistor

Semiconductor fabrication process including silicide stringer removal processing

Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing

Confined spacers for double gate transistor semiconductor fabrication process