Karlsruhe
Germany
22
2014-10-09
The entities that hold a legal rights for patent applications filed by inventor Munch Robert:
Robert Munch from Karlsruhe, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Multi-core processor having disabled cores
#2 | 2011-01-13RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL
#3 | 2010-11-11I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
#4 | 2010-04-01I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
#5 | 2009-12-03Data processor having disabled cores
#6 | 2009-09-01Method and system for alternating between programs for execution by cells of an integrated circuit
#7 | 2009-07-21Runtime configurable arithmetic and logic cell
#8 | 2009-06-18PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)
#9 | 2009-06-11Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
#10 | 2009-06-04PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)
#11 | 2008-09-11I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
#12 | 2008-01-10Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
#13 | 2007-11-01I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
#14 | 2007-07-10I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
#15 | 2007-06-26Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells
#16 | 2007-02-06Run-time reconfiguration method for programmable units
#17 | 2006-04-25Method of self-synchronization of configurable elements of a programmable module
#18 | 2006-04-11Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
#19 | 2006-03-07Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
#20 | 2006-02-09Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
#21 | 2005-11-22Method of self-synchronization of configurable elements of a programmable unit
#22 | 2005-11-17Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
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