Michael A. Blake

TARGET CHIP-CONTROLLED DATA PREFETCH FOR ACCELERATOR SHARING

Castout handling in a distributed cache topology

Shadow pointer directory in an inclusive hierarchical cache

Coherent cache with simultaneous data requests in same addressable index

Multilevel cache eviction management

Modified central serialization of requests in multiprocessor systems

Efficient remote resource allocation within an SMP broadcast scope maintaining fairness between operation types

NON-DISRUPTIVE CLEARING OF VARYING ADDRESS RANGES FROM CACHE

NON-DISRUPTIVE CLEARING OF VARYING ADDRESS RANGES FROM CACHE

Non-disruptive clearing of varying address ranges from cache

DYNAMIC THROTTLING OF BROADCASTS IN A TIERED MULTI-NODE SYMMETRIC MULTIPROCESSING COMPUTER SYSTEM

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Operation interlocking in an address-sliced cache system

Ownership tracking updates across multiple simultaneous operations

Ownership tracking updates across multiple simultaneous operations

Deadlock avoidance in a multi-processor computer system with extended cache line locking

Non-disruptive clearing of varying address ranges from cache

Hot cache line fairness arbitration in distributed modular SMP system

Hot cache line arbitration

Non-disruptive clearing of varying address ranges from cache

Eliminate corrupted portions of cache during runtime

Dynamic array masking

Eliminate corrupted portions of cache during runtime

Eliminate corrupted portions of cache during runtime

Operations interlock under dynamic relocation of storage

Dynamic cache correction mechanism to allow constant access to addressable index

Storing data in a system memory for a subsequent cache flush

Bitline deletion

Bitline deletion

Dynamic cache correction mechanism to allow constant access to addressable index

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

Storing data in a system memory for a subsequent cache flush

Multilevel cache hierarchy for finding a cache line on a remote node

Multilevel cache hierarchy for finding a cache line on a remote node

System refresh in cache memory

EDRAM macro disablement in cache memory

NON-BLOCKING DATA MOVE DESIGN

EDRAM macro disablement in cache memory

Centralized serialization of requests in a multiprocessor system

Tracking dynamic memory reallocation using a single storage address configuration table

NON-BLOCKING DATA MOVE DESIGN

Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES

Cache coherency protocol with built in avoidance for conflicting responses

Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching

Storage system that prioritizes storage requests

Apparatus and method for improved data persistence within a multi-node system

Method for ensuring fairness among requests within a multi-node computer system

Coherency management for a “switchless” distributed shared memory computer system

Memory management for a symmetric multiprocessor computer system

Coherency management for a “switchless” distributed shared memory computer system

Topology for shared memory computer system

Bus protocol for a switchless distributed shared memory computer system