Timothy C. Bronson

Achieving high bandwidth on ordered direct memory access write stream into a processor cache

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Ownership tracking updates across multiple simultaneous operations

Ownership tracking updates across multiple simultaneous operations

Hot cache line arbitration

Granting exclusive cache access using locality cache coherency state

Maintaining order with parallel access data streams

Dynamic relocation of storage

Memory controlled operations under dynamic relocation of storage

Granting exclusive cache access using locality cache coherency state

Granting exclusive cache access using locality cache coherency state

Non-data inclusive coherent (NIC) directory for cache

Non-data inclusive coherent (NIC) directory for cache

Dynamic cache correction mechanism to allow constant access to addressable index

Storing data in a system memory for a subsequent cache flush

Dynamic cache correction mechanism to allow constant access to addressable index

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

Storing data in a system memory for a subsequent cache flush

Multilevel cache hierarchy for finding a cache line on a remote node

Multilevel cache hierarchy for finding a cache line on a remote node

System refresh in cache memory

EDRAM macro disablement in cache memory

Optimizing EDRAM refresh rates in a high performance cache architecture

NON-BLOCKING DATA MOVE DESIGN

EDRAM macro disablement in cache memory

Centralized serialization of requests in a multiprocessor system

NON-BLOCKING DATA MOVE DESIGN

Cache bank modeling with variable access and busy times

Optimizing EDRAM refresh rates in a high performance cache architecture

Concurrent refresh in cache memory