SYNOPSYS, INC.

Coordinating and controlling debuggers in a simulation environment

STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN

Simulation control techniques

Pipeline analog-to-digital converter stages with improved transfer function

Gain and dither capacitor calibration in pipeline analog-to-digital converter stages

Modeling of cell delay change for electronic design automation

Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers

High-voltage switch using three FETs

Equation based transient circuit optimization

Managing the configuration and functionality of a semiconductor design

Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagation

Modeling transition effects for circuit optimization

Sequential sizing in physical synthesis

RFID tag having non-volatile memory device having floating-gate FETs with different source-gate and drain-gate border lengths

Electronic device, system on chip and method for monitoring a data flow

Modeling mask errors using aerial image sensitivity

Parasitic extraction for semiconductors

Incremental concurrent processing for efficient computation of high-volume layout data

Executing a hardware simulation and verification solution

Automated circuit design