Inventor profile of:

ASHER BERKOVITZ

City:

KIRYAT ONO

Country:

Israel

Published Applications:

14

Last publication date:

2016-12-29

Top Assignees for applications by ASHER BERKOVITZ

The entities that hold a legal rights for patent applications filed by inventor BERKOVITZ ASHER:

Recent patent applications by BERKOVITZ ASHER

ASHER BERKOVITZ from KIRYAT ONO, IL has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-12-29
US20160377676A1
Physics

INTEGRATED CIRCUIT INCLUDING OVERLAPPING SCAN DOMAINS

#2 | 2016-10-27
US20160314240A1
Physics

Method and apparatus for validating a test pattern

#3 | 2015-12-03
US20150347655A1
Physics

Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium

#4 | 2015-12-03
US20150347653A1
Physics

Method and apparatus for calculating delay timing values for an integrated circuit design

#5 | 2015-11-26
US20150339427A1
Physics

Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit

#6 | 2015-11-26
US20150339413A1
Physics

Method and apparatus for performing logic synthesis

#7 | 2015-11-26
US20150338460A1
Physics

Method and control device for launch-off-shift at-speed scan testing

#8 | 2015-10-29
US20150310152A1
Physics

Method and apparatus for calculating delay timing values for an integrated circuit design

#9 | 2015-10-01
US20150276869A1
Physics

Method and apparatus for at-speed scan shift frequency test optimization

#10 | 2015-09-03
US20150247899A1
Physics

Scan test system with a test interface having a clock control unit for stretching a power shift cycle

#11 | 2015-08-27
US20150242544A1
Physics

Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit

#12 | 2015-07-16
US20150199468A1
Physics

Method and apparatus for selecting data path elements for cloning

#13 | 2014-11-27
US20140351781A1
Physics

Method for placing operational cells in a semiconductor device

#14 | 2014-10-30
US20140325461A1
Physics

Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis

InventorID:

956739 ⎘