Inventor profile of:

Jean Audet

City:

Granby

Country:

Canada

Published Applications:

24

Last publication date:

2020-09-03

Top Assignees for applications by Jean Audet

The entities that hold a legal rights for patent applications filed by inventor Audet Jean:

Recent patent applications by Audet Jean

Jean Audet from Granby, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-09-03
US20200279840A1
Electricity

Photonics package with face-to-face bonding

#2 | 2020-07-30
US20200245466A1
Electricity

Thin film capacitors for core and adjacent build up layers

#3 | 2020-04-02
US20200104454A1
Physics

Automated generation of surface-mount package design

#4 | 2019-11-28
US20190362049A1
Physics

Semiconductor package floating metal checks

#5 | 2019-06-06
US20190172787A1
Electricity

High-density chip-to-chip interconnection with silicon bridge

#6 | 2019-05-16
US20190150287A1
Electricity

Thin film capacitors for core and adjacent build up layers

#7 | 2019-04-04
US20190102505A1
Physics

Semiconductor package floating metal checks

#8 | 2016-12-22
US20160372337A1
Electricity

Interposer with lattice construction and embedded conductive metal structures

#9 | 2016-07-21
US20160211481A1
Electricity

Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance

#10 | 2016-07-21
US20160211229A1
Electricity

Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance

#11 | 2016-07-21
US20160210398A1
Physics

Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance

#12 | 2016-06-16
US20160172290A1
Electricity

Interposer with lattice construction and embedded conductive metal structures

#13 | 2016-06-16
US20160172288A1
Electricity

Interposer with lattice construction and embedded conductive metal structures

#14 | 2013-02-21
US20130043060A1
Electricity

Method for forming coreless flip chip ball grid array (FCBGA) substrates and such substrates formed by the method

#15 | 2009-01-27
US12111196
-

Method for determining the impact of layer thicknesses on laminate warpage

#16 | 2008-12-18
US20080308923A1
Electricity

High performance chip carrier substrate

#17 | 2008-12-04
US20080296054A1
Electricity

High performance chip carrier substrate

#18 | 2008-11-27
US20080290510A1
Electricity

Apparatus for crack prevention in integrated circuit packages

#19 | 2008-03-06
US20080054482A1
Electricity

Semiconductor package having non-aligned active vias

#20 | 2008-01-17
US20080012583A1
Physics

Power grid structure to optimize performance of a multiple core processor

#21 | 2007-09-11
US11426646
-

Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip

#22 | 2007-08-02
US20070175658A1
Electricity

High performance chip carrier substrate

#23 | 2006-03-21
US10738799
-

Concurrent electrical signal wiring optimization for an electronic package

#24 | 2005-05-26
US20050109535A1
Electricity

High performance chip carrier substrate

InventorID:

96240 ⎘