Inventor profile of:

Jong-Wook Lee

City:

Gyeonggi-do

Country:

South Korea

Published Applications:

34

Last publication date:

2019-11-07

Top Assignees for applications by Jong-Wook Lee

The entities that hold a legal rights for patent applications filed by inventor Lee Jong-Wook:

Recent patent applications by Lee Jong-Wook

Jong-Wook Lee from Gyeonggi-do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-11-07
US20190338284A1
Chemistry; metallurgy

COMPLEX FOR DRUG DELIVERY AND STABILIZATION AND PREPARATION METHOD THEREOF

#2 | 2014-11-13
US20140336229A1
Human necessities

Pharmaceutical composition for preventing or treating hyperlipidemia

#3 | 2014-11-13
US20140336228A1
Human necessities

Pharmaceutical composition for preventing or treating hypertriglyceridemia or hypertriglyceridemia-associated diseases

#4 | 2012-05-17
US20120119383A1
Electricity

Stacked integrated circuit package having recessed sidewalls

#5 | 2011-12-08
US20110300704A1
Electricity

Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same

#6 | 2011-06-02
US20110126811A1
Electricity

Ignition coil of engine

#7 | 2011-05-12
US20110111610A1
Electricity

Connector for vehicle effectively removing or reducing noise and providing secure connection

#8 | 2010-12-30
US20100330753A1
Electricity

METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING A TRANSCRIPTION-PREVENTING PATTERN

#9 | 2010-06-24
US20100159689A1
Electricity

Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same

#10 | 2010-05-06
US20100109164A1
Electricity

Stacked integrated circuit packages that include monolithic conductive vias

#11 | 2009-09-03
US20090221133A1
Electricity

Methods of Fabricating Silicon on Insulator (SOI) Wafers

#12 | 2009-05-21
US20090130826A1
Electricity

Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer

#13 | 2009-04-23
US20090104759A1
Electricity

Methods of manufacturing semiconductor devices including a doped silicon layer

#14 | 2008-12-18
US20080308845A1
Electricity

Heterogeneous Group IV Semiconductor Substrates

#15 | 2008-11-27
US20080293224A1
Electricity

METHOD OF FORMING A DIODE AND METHOD OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME

#16 | 2008-10-09
US20080248628A1
Electricity

Methods of Forming Integrated Circuit Devices Having Single Crystal Semiconductor FIN Structures that Function as Device Active Regions

#17 | 2008-09-11
US20080217689A1
Electricity

SEMICONDUCTOR DEVICES HAVING SILICON-ON-INSULATOR (SOI) SUBSTRATES AND METHODS OF MANUFACTURING THE SAME

#18 | 2008-07-31
US20080179665A1
Electricity

Semiconductor Memory Devices and Methods of Forming the Same

#19 | 2008-04-24
US20080093601A1
Electricity

Integrated circuit devices including a transcription-preventing pattern

#20 | 2008-03-20
US20080070372A1
Electricity

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

#21 | 2008-01-17
US20080014726A1
Electricity

Methods of fabricating semiconductor devices having laser-formed single crystalline active structures

#22 | 2007-10-04
US20070231976A1
Electricity

Method for fabricating a semiconductor device

#23 | 2007-09-20
US20070218607A1
Electricity

Methods of forming single crystalline layers and methods of manufacturing semiconductor devices having such layers

#24 | 2007-01-11
US20070006800A1
Chemistry; metallurgy

METHODS OF SELECTIVELY FORMING AN EPITAXIAL SEMICONDUCTOR LAYER USING ULTRA HIGH VACUUM CHEMICAL VAPOR DEPOSITION TECHNIQUE AND BATCH-TYPE ULTRA HIGH VACUUM CHEMICAL VAPOR DEPOSITION APPARATUS USED THEREIN

#25 | 2006-09-21
US20060211262A1
Electricity

Methods of laterally forming single crystalline thin film regions from seed layers

#26 | 2006-04-13
US20060079056A1
Electricity

Semiconductor structures having a strained silicon layer on a silicon-germanium layer and related fabrication methods

#27 | 2006-03-16
US20060057821A1
Electricity

Low temperature methods of etching semiconductor substrates

#28 | 2005-12-08
US20050272190A1
Electricity

Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices

#29 | 2005-11-10
US20050250279A1
Electricity

Methods of forming semiconductor devices having buried oxide patterns

#30 | 2005-11-10
US20050248035A1
Electricity

Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same

#31 | 2005-10-06
US20050218395A1
Electricity

Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods

#32 | 2005-09-15
US20050199948A1
Electricity

Fin field effect transistors with epitaxial extension layers and methods of forming the same

#33 | 2005-09-15
US20050199920A1
Electricity

Fin field effect transistors with low resistance contact structures

#34 | 2005-04-07
US20050073061A1
Electricity

Static random access memories including a silicon-on-insulator substrate

InventorID:

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