Inventor profile of:

Wei Cao

City:

San Jose, California

Country:

United States

Published Applications:

23

Last publication date:

2023-11-02

Top Assignees for applications by Wei Cao

The entities that hold a legal rights for patent applications filed by inventor Cao Wei:

Recent patent applications by Cao Wei

Wei Cao from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-11-02
US20230350966A1
Physics

Communicating URL categorization information

#2 | 2023-04-06
US20230108362A1
Physics

Key-value storage for URL categorization

#3 | 2021-02-18
US20210049226A1
Physics

Communicating URL categorization information

#4 | 2021-02-18
US20210049207A1
Physics

Key-value storage for URL categorization

#5 | 2020-01-28
US14546850
Electricity

Implementation of LLR biasing method in non-binary iterative decoding

#6 | 2017-07-18
US12859090
Electricity

Network services resource management

#7 | 2016-07-21
US20160211442A1
Electricity

Magnetic tunnel junction for MRAM applications

#8 | 2014-12-09
US13660659
-

Implementation of LLR biasing method in non-binary iterative decoding

#9 | 2014-10-16
US20140306305A1
Electricity

Magnetic tunnel junction for MRAM applications

#10 | 2013-11-14
US20130299823A1
Electricity

Magnetic tunnel junction for MRAM applications

#11 | 2013-10-08
US13741705
-

System and method of adjusting current drawn by an integrated circuit based on frequencies of clock signals

#12 | 2013-02-21
US20130043471A1
Electricity

Magnetic tunnel junction for MRAM applications

#13 | 2013-01-15
US13090600
-

Systems and methods for controlling power supply current using clock gating

#14 | 2012-11-08
US20120280337A1
Electricity

Composite free layer within magnetic tunnel junction for MRAM applications

#15 | 2012-07-19
US20120181537A1
Electricity

Magnetic tunnel junction for MRAM applications

#16 | 2012-04-12
US20120085728A1
Performing operations; transporting

Process for MEMS scanning mirror with mass remove from mirror backside

#17 | 2011-06-09
US20110133300A1
Electricity

Bottom electrode for MRAM device

#18 | 2011-03-31
US20110076785A1
Electricity

Process to fabricate bottom electrode for MRAM device

#19 | 2008-04-17
US20080090307A1
Electricity

Bottom electrode for MRAM device and method to fabricate it

#20 | 2007-12-06
US20070281427A1
Electricity

Bottom conductor for integrated MRAM

#21 | 2007-09-20
US20070215911A1
Electricity

Magnetic tunnel junction patterning using Ta/TaN as hard mask

#22 | 2007-03-01
US20070045758A1
Electricity

Bottom conductor for integrated MRAM

#23 | 2006-10-17
US11231674
-

Method of fabricating contact pad for magnetic random access memory

InventorID:

97050 ⎘