Mehul D. SHROFF

SEMICONDUCTOR CIRCUIT WITH BACK-SIDE PARTIAL-SUBSTRATE POWER RAILS

INTERCONNECT STRUCTURE WITH RELAXED VIA-CORNER SLOPE

LOW-K INTERCONNECT DIELECTRIC BY SELECTIVE IMPLANTATION

ELECTRONIC DEVICES INCLUDING A SIDEWALL STRUCTURE AND METHODS OF FORMATION THEREOF

LATCH-UP PREVENTION WITH WELL-TIE EXTENSION USING SELECTIVE WELL DOPING

INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS

INTEGRATED CIRCUIT WITH OVERLAPPING STRESSORS

SYSTEM HAVING SINGLE-EVENT LATCH-UP DETECTION AND MITIGATION

Packaged integrated circuit having a photodiode and a resistive memory

Magnetic attack detection in a magnetic random access memory (MRAM)

Post contact air gap formation

Multigate transistor

Method of forming inter-level dielectric structures on semiconductor devices

Semiconductor device with graphene encapsulated metal and method therefor

Semiconductor device with graphene encapsulated metal and method therefor

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

Solar cell powered integrated circuit device and method therefor

Method of forming inter-level dielectric structures on semiconductor devices

METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR TRANSISTOR MEMORY-BASED DEVICES

Though-substrate vias (TSVs) and method therefor

Semiconductor device with upset event detection and method of making

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit

Applications for nanopillar structures

Voltage and current limits for electronic device based on temperature range

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Method for forming a split-gate device

Method for forming a split-gate device

Method of making a logic transistor and non-volatile memory (NVM) cell

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING

Method for forming a split-gate device

Thin beam deposited fuse

3D device packaging using through-substrate posts

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Techniques for electromigration stress mitigation in interconnects of an integrated circuit design

Stress migration mitigation

Methods of making semiconductor devices with non-volatile memory cells

Capping layer interface interruption for stress migration mitigation

Method and system for recovering from transistor aging using heating

Method for forming an electrical connection between metal layers

Fuse/resistor utilizing interconnect and vias and method of making

Semiconductor device with embedded heat spreading

Semiconductor device with vias on a bridge connecting two buses

Multi-layer process-induced damage tracking and remediation

Method for forming an integrated circuit having a programmable fuse

Implant for performance enhancement of selected transistors in an integrated circuit

Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique

Semiconductor devices with non-volatile memory cells

Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage

Systems and methods for determining aging damage for semiconductor devices

Method of making a logic transistor and a non-volatile memory (NVM) cell

Method for forming an electrical connection between metal layers

Method and system for derived layer checking for semiconductor device design

Method for forming an electrical connection between metal layers

Method for forming an electrical connection between metal layers

Applications for nanopillar structures

Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric

Techniques for electromigration stress determination in interconnects of an integrated circuit

Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules

Device matching tool and methods thereof

Via placement and electronic circuit design processing method and electronic circuit design utilizing same

Mismatch verification device and methods thereof

Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Non-volatile memory (NVM) and logic integration

Semiconductor device with embedded heat spreading

Semiconductor device with heat dissipation

Logic transistor and non-volatile memory cell integration

Logic transistor and non-volatile memory cell integration

Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic

Non-volatile memory cell and logic transistor integration

Techniques for electromigration stress determination in interconnects of an integrated circuit

Methods of making logic transistors and non-volatile memory cells

Non-volatile memory (NVM) and logic integration

Non-volatile memory (NVM) and logic integration

Non-volatile memory (NVM) and logic integration

Method of protecting against via failure and structure therefor

Logic and non-volatile memory (NVM) integration

Semiconductor device with vias on a bridge connecting two buses

Capacitive sensor radiation measurement

Incident capacitive sensor

Method and system for physical verification using network segment current

Implant for performance enhancement of selected transistors in an integrated circuit

Memory with discrete storage elements

Method of making a semiconductor device as a capacitor

Semiconductor device structure as a capacitor

Decoupling capacitors recessed in shallow trench isolation

Isolated capacitors within shallow trench isolation

Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor

Non-volatile memory and logic circuit process integration

Non-volatile memory and logic circuit process integration

Methods of making multi-state non-volatile memory cells

Method for integrating a non-volatile memory (NVM)

Non-volatile memory and logic circuit process integration

Lateral capacitor and method of making

Patterning a gate stack of a non-volatile memory (NVM) with simultaneous etch in non-NVM area

Patterning a gate stack of a non-volatile memory (NVM) using a dummy gate stack

Method for reducing plasma discharge damage during processing

Process of forming an electronic device including insulating layers having different strains