Anindya PODDAR

PACKAGES WITH ELECTRICAL FUSES

THERMAL BAR STRUCTURE IN AN EMBEDDED TRACE SUBSTRATE

STACKED DIE ELECTRONIC DEVICE WITH INTEGRATED MAGNETICS

SEMICONDUCTOR PACKAGE MOLD COMPOUND DAMS

Semiconductor-based Strain Sensor

CHIP ON LEAD DEVICE AND MANUFACTURING METHOD

ISOLATION FOR CHIP ON LEAD DEVICE AND MANUFACTURING METHOD

MICROELECTRONIC DEVICE PACKAGE WITH INTEGRAL ANTENNA MODULE AND SEMICONDUCTOR DEVICE

MICROELECTRONIC DEVICE PACKAGE WITH HYBRID ISOLATION LAMINATE

INTEGRATED CIRCUIT (IC) WITH EXPOSED ACTIVE CIRCUITRY

HALL SENSOR WITH MAGNETIC CONCENTRATORS

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIRCUIT PACKAGE

PACKAGES WITH ENHANCED HEAT DISSIPATION AND PARASITIC INDUCTANCE MITIGATION

CONDUCTIVE MEMBERS ATOP SEMICONDUCTOR PACKAGES

HYBRID QUAD FLAT PACKAGE ELECTRONIC DEVICE

METAL RIBS IN ELECTROMECHANICAL DEVICES

FRAME DESIGN IN EMBEDDED DIE PACKAGE

Converter Package with Integrated Inductor

PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE

ELECTRONIC DEVICE WITH A REINFORCING LAYER

DIE ISOLATION WITH CONFORMAL COATING

SEMICONDUCTOR DEVICE PACKAGE WITH THERMAL PAD

PACKAGES WITH ELECTRICAL FUSES

MICROELECTRONIC DEVICE PACKAGE WITH INTEGRAL ANTENNA MODULE AND SEMICONDUCTOR DEVICE

Metal ribs in electromechanical devices

POWER MODULE PACKAGE WITH MAGNETIC MOLD COMPOUND

ISOLATION PACKAGE WITH HIGH THERMAL CONDUCTIVITY

Conductive members atop semiconductor packages

FABRICATION PROCESS FOR PROTECTING CIRCUIT COMPONENTS

Semiconductor package having an interdigitated mold arrangement

Semiconductor device package with thermal pad

WAFER LEVEL PROCESSING FOR MICROELECTRONIC DEVICE PACKAGE WITH CAVITY

FLIP CHIP PACKAGED DEVICES WITH THERMAL INTERPOSER

Packages with electrical fuses

Package for stress sensitive component and semiconductor device

Flip chip packaged devices with thermal pad

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIRCUIT PACKAGE

Semiconductor package with isolated heat spreader

Embedded die packaging with integrated ceramic substrate

Metal ribs in electromechanical devices

Semiconductor package with isolated heat spreader

Frame design in embedded die package

Electronic package for integrated circuits and related methods

Integrated circuit backside metallization

Bump bond structure for enhanced electromigration performance

Packaged semiconductor devices for high voltage with die edge protection

Electronic device with double-sided cooling

Integrated circuit backside metallization

Stress buffer layer in embedded package

Fan-out electronic device

Copper passivation

High Voltage Flip-Chip On Lead (FOL) Package

Additive deposition low temperature curable magnetic interconnecting layer for power components integration

INKJET PRINTED ELECTRONIC COMPONENTS

Embedded die packaging with integrated ceramic substrate

High voltage flip-chip on lead (FOL) package

Packaged semiconductor devices for high voltage with die edge protection

Printed repassivation for wafer chip scale packaging

Bump bond structure for enhanced electromigration performance

Stress buffer layer in embedded package

INTEGRATED CIRCUIT (IC) PACKAGES WITH SHIELDS AND METHODS OF PRODUCING THE SAME

Semiconductor systems having dual leadframes

METHOD AND STRUCTURE TO ELIMINATE SUBSTRATE COUPLING IN COMMON DRAIN DEVICES

Electronic package for integrated circuits and related methods

Embedded die package multichip module

Integration of a passive component in an integrated circuit package

Integration of a passive component in a cavity of an integrated circuit package

INTEGRATION OF A PASSIVE COMPONENT IN A CAVITY OF AN INTEGRATED CIRCUIT PACKAGE

Forming integrated inductors and transformers with embedded magnetic cores

Semiconductor systems having premolded dual leadframes

Open cavity package using chip-embedding technology

DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND

DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND

FORMING INTEGRATED INDUCTORS AND TRANSFORMERS WITH EMBEDDED MAGNETIC CORES

Multilayer high voltage isolation barrier in an integrated circuit

METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES

MICRO SURFACE MOUNT DEVICE PACKAGING

Micro surface mount device packaging

Thermally efficient integrated circuit package

Method and apparatus for achieving galvanic isolation in package having integral isolation medium

LOW PROFILE PACKAGE AND METHOD

Lead frame interconnect scheme with high power density

Foil-based method for packaging intergrated circuits

LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS

Foil based semiconductor package

WAFER LEVEL METHOD OF FORMING SIDE FIBER INSERTION OPTOELECTRONIC PACKAGES

Wafer level optoelectronic package with fiber side insertion

THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS

Inkjet printed leadframe

Integrated circuit package

METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH THIN METAL CONTACTS

Methods and systems for packaging integrated circuits with integrated passive components

Inkjet printed leadframes

I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRATED CIRCUIT DEVICES

Method of packaging integrated circuits

Integrated circuit package

Intergrated circuit packaging with improved die bonding

Bond pad stacks for ESD under pad and active under pad bonding

Gang flipping for IC packaging

GANG FLIPPING FOR FLIP-CHIP PACKAGING