🔗 Permalink

Inventor profile of:

Michael B. Solka

City:

Austin, Texas

Country:

United States

Published Applications:

27

Last publication date:

2025-05-22

Top Assignees for applications by Michael B. Solka

The entities that hold a legal rights for patent applications filed by inventor Solka Michael B.:

COHERENT LOGIX INCORPORATED 20 Austin, TX United States
Coherent Logix, Inc. 1 Austin, TX United States
HyperX Logic, Inc. 1 Austin, TX United States

Recent patent applications by Solka Michael B.

Michael B. Solka from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-05-22

US20250168927A1

Home Power Distribution with Multiphase Bridging

#2 | 2024-12-26

US20240427973A1

Modular Design Flow

#3 | 2023-08-31

US20230276535A1

Home power distribution with multiphase bridging

#4 | 2023-05-18

US20230153117A1

Memory-network processor with programmable optimizations

#5 | 2022-02-24

US20220061127A1

Home power distribution with multiphase bridging

#6 | 2021-07-08

US20210208895A1

Memory-network processor with programmable optimizations

#7 | 2020-09-24

US20200302090A1

Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric

#8 | 2020-08-27

US20200273484A1

Birdwatching System

#9 | 2020-06-04

US20200178355A1

Home power distribution with multiphase bridging

#10 | 2020-04-16

US20200117521A1

Processing system with interspersed processors with multi-layer interconnect

#11 | 2019-12-05

US20190369990A1

Memory-network processor with programmable optimizations

#12 | 2019-05-23

US20190155666A1

Processing system with interspersed processors with multi-layer interconnection

#13 | 2018-09-27

US20180276416A1

Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric

#14 | 2018-09-20

US20180267846A1

Processing system with interspersed processors with multi-layer interconnection

#15 | 2017-10-05

US20170286196A1

Processing system with interspersed processors with multi-layer interconnection

#16 | 2016-11-17

US20160335218A1

Processing system with interspersed processors with multi-layer interconnection

#17 | 2016-11-10

US20160328231A1

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

#18 | 2016-08-11

US20160232357A1

Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric

#19 | 2016-07-07

US20160196234A1

Processing system with synchronization instruction

#20 | 2015-12-10

US20150355596A1

Three dimensional display system

#21 | 2015-01-22

US20150026451A1

Multiprocessor fabric having configurable communication that is selectively disabled for secure processing

#22 | 2014-11-27

US20140351551A1

Memory-network processor with programmable optimizations

#23 | 2014-06-12

US20140164735A1

Processing system with synchronization instruction

#24 | 2014-05-22

US20140143520A1

Processing system with interspersed processors with multi-layer interconnect

#25 | 2013-12-26

US20130343450A1

Distributed architecture for encoding and delivering video content

#26 | 2013-02-21

US20130044105A1

Three dimensional display compute system

#27 | 2012-05-31

US20120137119A1

Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration

InventorID:

98274 ⎘