Boise, Idaho
United States
27
2025-08-21
The entities that hold a legal rights for patent applications filed by inventor VIOLETTE MICHAEL:
MICHAEL VIOLETTE from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
APPARATUS HAVING TRANSISTORS WITH RAISED EXTENSION REGIONS AND SEMICONDUCTOR FINS
#2 | 2023-06-01Capacitor structures and apparatus containing such capacitor structures
#3 | 2022-06-09Transistors with raised extension regions and semiconductor fins
#4 | 2021-10-14Methods of forming capacitor structures
#5 | 2020-12-31Capacitor structures
#6 | 2020-09-24Apparatus having integrated circuit well structures of vertical and/or retrograde profiles
#7 | 2019-07-04Methods of forming integrated circuit well structures
#8 | 2017-09-14Method for fabricating a metal high-k gate stack for a buried recessed access device
#9 | 2016-07-14Method for fabricating a metal high-k gate stack for a buried recessed access device
#10 | 2015-07-02Method for fabricating a metal high-k gate stack for a buried recessed access device
#11 | 2014-12-04Method for fabricating a metal high-k gate stack for a buried recessed access device
#12 | 2011-01-20Isolation trenches for memory devices
#13 | 2008-06-05Isolation trenches for memory devices
#14 | 2007-06-21ANGLED IMPLANT TO IMPROVE HIGH CURRENT OPERATION OF BIPOLAR TRANSISTORS
#15 | 2007-04-03Angled implant to improve high current operation of bipolar transistors
#16 | 2007-03-22NAND memory arrays
#17 | 2007-03-22Isolation trenches for memory devices
#18 | 2006-11-16NAND memory arrays
#19 | 2006-02-23NAND memory arrays and methods
#20 | 2006-01-12Memory cells and select gates of NAND memory arrays
#21 | 2005-12-29Isolation trenches for memory devices
#22 | 2005-12-29Isolation trenches for memory devices
#23 | 2005-12-29Formation of memory cells and select gates of NAND memory arrays
#24 | 2005-11-24Select lines for NAND memory devices
#25 | 2005-09-29Method of forming select lines for NAND memory devices
#26 | 2005-09-15Interconnecting conductive layers of memory devices
#27 | 2005-03-01Interconnecting conductive layers of memory devices
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