Xiaolin Wang

EFFICIENT HIGH PERFORMANCE SCALABLE PIPELINED SEARCHING METHOD USING VARIABLE STRIDE MULTIBIT TRIES

Hierarchical multi-core processor and method of programming for efficient data processing

Dynamically reconfigurable hybrid circuit-switched and packet-switched network architecture

Instruction set design, control and communication in programmable microprocessor cores and the like

Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions

Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing

Method of and apparatus for correcting errors in data packet flow streams as in closed ring sequential address generators and the like without data flow stream interruption

Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor

Method and apparatus for fairly sharing excess bandwidth and packet dropping amongst subscribers of a data network

Method of and apparatus for variable length data packet transmission with configurable adaptive output scheduling enabling transmission on the same transmission link(s) of differentiated services for various traffic types