Stackable semiconductor package including laminate interposer

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

Not Applicable

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to integrated circuit chip package technology and, more particularly, to a semiconductor package which includes an embedded laminate interposer configured to allow a mating semiconductor package to be mounted and electrically connected thereto.

2. Description of the Related Art

Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.

The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device.

Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.

Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages on top of each other, or to stack individual semiconductor devices or other devices within the package body of the semiconductor package. However, when attempting to integrate a large number of devices such as memory chips into a vertical stack, test yield loss typically becomes higher as more such devices are assembled in a single package. As a result, it becomes desirable to use multiple packages which each contain a subset of the memory chips or devices to be integrated vertically. Existing solutions for package stacking such as straddle mount laminate BGA or stacked die TSOP often do not meet form factor requirements. Therefore, a new solution is needed. The present invention is an extension of the stacking solution for space efficiency in that it is directed to, among other things, a semiconductor package which includes an embedded laminate interposer configured to allow a mating semiconductor package to be mounted and electrically connected thereto. In this regard, the present invention provides a three-dimensional packaging solution which is required for, among other things, high density NAND Flash integration. These, as well as other features and attributes of the present invention will be discussed in more detail below.

BRIEF SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, there is provided a two sided interconnect structure (i.e., a laminate interposer) which is mounted to a semiconductor package leadframe or substrate prior to molding the package body of the semiconductor package. During the molding process, the top of the laminate interposer is protected such that the top surface of the interposer is exposed subsequent to the completion of the molding process. In this manner, electrical signals can be routed from the package leadframe or substrate to the top surface of the package body of the semiconductor package. Subsequently, a mating package can be mounted on top of the underlying package by way of a ball grid array (BGA) interconnect or other type of interconnect. The interposer may be mounted to the package leadframe or substrate using a standard BGA interconnect method. During molding of the package body, the mold compound will flow underneath the interposer and between the BGA joints, thus helping to lock the interposer in place in the completed semiconductor package. The interposer may be mounted to a substrate strip with an array of units so that a single interposer strip or frame is attached to adjacent units. During singulation (i.e., the separation of the completed units or semiconductor packages from each other), the interposer is separated so that the interposer is exposed on the side of the semiconductor package. Locking features may be added to the laminate interposer to improve reliability.

In accordance with another aspect of the present invention, there is provided a chip stack wherein multiple semiconductor packages (e.g., QFN packages) are stacked together using a laminate interposer. The leads of the semiconductor packages integrated into the stack are extended to provide a mounting surface for the laminate interposer. The laminate interposer provides routing between the bottom and top packages in the stack. This is required to route chip-select signals in such a way that all the semiconductor packages in the stack may have identical bond diagrams.

The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:

FIG. 1 is a top plan view of a semiconductor package constructed in accordance with a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the semiconductor package of the first embodiment of the present invention taken along line 2-2 of FIG. 1;

FIG. 3 is a cross-sectional view of a pair of semiconductor packages constructed in accordance with the first embodiment as arranged in a stacked configuration;

FIG. 4 is a cross-sectional view of a semiconductor package constructed in accordance with a second embodiment of the present invention;

FIG. 5 is a cross-sectional view of a pair of semiconductor packages constructed in accordance with the second embodiment as arranged in a stacked configuration; and

FIG. 6 is a cross-sectional view of a pair of semiconductor packages as arranged in a stacked configuration through the use of an interposer constructed in accordance with a third embodiment of the present invention.

Common reference numerals are used throughout the drawings and detailed description to indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes of illustrating various embodiments of the present invention only, and not for purposes of limiting the same, FIGS. 1 and 2 depict a semiconductor package 10 constructed in accordance with a first embodiment of the present invention. The semiconductor package 10 comprises a leadframe 12 which itself includes a die attach pad or die pad 14. In the semiconductor package 10, the die pad 14 has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the die pad 14 defines a generally planar top surface 16, and an opposed, generally planar bottom surface 18.

In addition to the die pad 14, the leadframe 12 of the semiconductor package 10 comprises a plurality of leads 20. In the semiconductor package 10, the leads 20 are segregated into two sets, with the leads 20 of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the die pad 14. Each lead 20 preferably defines a generally planar top surface 22, and a generally planar bottom surface 24 which is disposed in opposed relation to the top surface 22. In addition to the top and bottom surfaces 22, 24, each lead 20 further defines a shoulder or shelf 26 which is recessed relative to the bottom surface 24, and extends in opposed relation to the top surface 22. The shelf 26 of each lead 20 also extends to the innermost end thereof, i.e., the end disposed closest to the die pad 14.

The leadframe 12 of the semiconductor package 10 is preferably fabricated from a conventional metal material, such as copper or copper alloy. The formation of the shelves 26 within the leads 20 and the top surface 16 of the die pad 14 is preferably facilitated by subjecting a metal plate from which the leadframe 12 is typically formed to a partial etching process. More particularly, each of the opposed, generally planar faces or sides of such metal plate preferably has an etch mask applied thereto in a manner wherein the subsequent application of a suitable etchant to the metal plate will effectively remove metal material therefrom as facilitates the formation of the top surface 16 of the die pad 14 and the recessed shelves 26 of the leads 20. Such etching process may also be used to facilitate the formation of the die pad 14 and leads 20 themselves from the original metal plate, or may be implemented so as to facilitate the formation of the top surface 16 and shelves 26 subsequent to the die pad 14 and leads 20 being defined by the completion of a stamping process upon the original metal plate.

As is further seen in FIG. 2, the partial etching process to which the die pad 14 and leads 20 are subjected is preferably completed in a manner wherein the thickness of the die pad 14 between the top and bottom surfaces 16, 18 thereof is approximately one-half of the thickness of each of the leads 20 between the top and bottom surfaces 22, 24 thereof. Similarly, the thickness of each lead 20 between the top surface 22 and the shelf 26 thereof is approximately one-half of the thickness of each lead 20 between the top and bottom surfaces 22, 24 thereof. Thus, in the leadframe 12, the bottom surfaces 18, 24 of the die pad 14 and leads 20 extend in generally co-planar relation to each other. Though the top surface 16 of the die pad 14 and the shelves 26 of the leads 20 are typically not perfectly planar due to their formation as a result of the completion of a chemical etching process, such surfaces also extend in generally co-planar relation to each other in the manner shown in FIG. 2. Though not shown, those of ordinary skill in the art will recognize that the die pad 14 may be alternately configured to have a thickness similar to that of the leads 20, such that the top surface 16 of the die pad 14 and the top surfaces 22 of the leads 20 extend in substantially coplanar relation to each other. Further, it is contemplated that that the die pad 14 may be formed to include a recessed shelf similar to the shelf 26 of each of the leads 20 or another suitable locking feature to assist in the firm interlock thereof to a package body 60 of the semiconductor package 10 which is described in detail below. Still further, it is also contemplated that the bottom surface 18 of the die pad 14 may included a recessed portion for providing a surface for adhesively bonding two stacked packages to each other, as will also be described below.

Attached to the top surface 16 of the die pad 14 is a die stack 28 of the semiconductor package 10. The die stack 28 comprises a plurality of individual semiconductor dies 30 which are arranged in a stacked configuration. In this regard, each of the semiconductor dies 30 in the die stack 28 is secured to the semiconductor die 30 below it by a layer 32 of a suitable adhesive. Similarly, the attachment of the lowermost semiconductor die 30 in the die stack 28 to the top surface 16 of the die pad 14 is facilitated by an additional adhesive layer 32. As shown in FIG. 2, four semiconductor dies 30 are depicted as being included in the die stack 28. However, those of ordinary skill in the art will recognize that the die stack 28 may be assembled to include fewer or greater than the four semiconductor dies 30 depicted in FIG. 2. In the semiconductor package 10, the pads or terminals of each of the semiconductor dies 30 of the die stack 28 are electrically connected to the leads 20 through the use of conductive wires 34. The conductive wires 34 may be fabricated from aluminum, copper, gold, silver or a functional equivalent.

The semiconductor package 10 of the present invention further comprises a laminate interposer 36 which is mounted and electrically connected to the top surfaces 22 of the leads 20. As seen in FIGS. 1 and 2, the interposer 36 comprises a first segment 36a which is electrically connected to each of the leads 20 of one of the sets thereof, and a separate second segment 36b which is electrically connected to each of the leads 20 of the remaining set thereof. The first and second segments 36a, 36b of the interposer 36 are identically configured to each other and, in the completed semiconductor package 10, extend in spaced, generally parallel relation to each other.

Each of the interposer segments 36a, 36b of the interposer 36 comprises an interposer body 38 having a top surface 40, a bottom surface 42, an opposed pair of longitudinal side surfaces 44, and an opposed pair of lateral side surfaces 46. Embedded within the interposer body 38 of each of the first and second segments 36a, 36b is a plurality of top pads 48 and bottom pads 50. The top and bottom pads 48, 50 embedded within the interposer body 38 of each of the first and second segments 36a, 36b are segregated into multiple pairs, with the top pad 48 of each pair being disposed in spaced, substantial vertical alignment with the bottom pad 50 of the same pair. As seen in FIG. 2, the top and bottom pads 48, 50 of each pair within each of the first and second segments 36a, 36b are electrically connected to each other by one or more conductive vias 52 which extend through the interposer body 38 substantially perpendicularly between the top and bottom pads 48, 50 of the corresponding pair. The top and bottom pads 48, 50 of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s) 52 extending therebetween. Those of ordinary skill in the art will recognize that the top and bottom pads 48, 50 of each pair need not necessarily be in exact vertical alignment, and that some degree of juxtaposition therebetween is contemplated to fall within the scope of the present invention.

As further seen in FIGS. 1 and 2, formed in the top surface 40 of the interposer body 38 of each of the first and second segments 36a, 36b of the laminate interposer 36 is a plurality of top openings 54. Similarly, formed in the bottom surface 42 of the interposer body 38 of each of the first and second segments 36a, 36b is a plurality of bottom openings 56. Though depicted as being circularly configured, those of ordinary skill in the art will recognize that the top and/or bottom openings 54, 56 may be formed to have alternative shapes (e.g., square, rectangular). Exposed within each of the top openings 54 is a respective one of the top pads 48, while exposed within each of the bottom openings 56 is a respective one of the bottom pads 50. In the semiconductor package 10, each exposed bottom pad 50 in each of the first and segments 36a, 36b is electrically connected to the top surface 22 of a respective one of the leads 20 of the corresponding set thereof by a solder ball 58. It is contemplated that a conductive adhesive or solder paste may be used as an alternative to the solder balls 58. As best seen in FIG. 2, such attachment is preferably facilitated such that one of the longitudinal side surfaces 44 of each of the first and second segments 36a, 36b extends in generally co-planar relation to the outermost, generally planar distal ends of the leads 20 of the corresponding set thereof.

In the semiconductor package 10, the die stack 28, wires 34, and portions of the die pad 14, leads 20 and first and second segments 36a, 36b of the laminate interposer 36 are encapsulated or covered by an encapsulant material which, upon hardening, forms a package body 60 of the semiconductor package 10. Also fully covered by the package body 60 are the solder balls 58 used to effectuate the electrical connection between the first and second segments 36a, 36b of the laminate interposer 36 and the first and second sets of leads 20 of the leadframe 12. The fully formed package body 60 has a generally quadrangular configuration and defines a generally planar top surface 62 and an opposed, generally planar bottom surface 64. In addition to the top and bottom surfaces 62, 64, the package body 60 also defines multiple side surfaces 66. The package body 60 is preferably formed such that the bottom surfaces 18, 24 of the die pad 14 and leads 20 are each exposed in and substantially flush with the bottom surface 64. The package body 60 is further formed such that the top surface 40 of the interposer body 38 of each of the first and second segments 36a, 36b is exposed in and substantially flush with the top surface 62, with one of the longitudinal side surfaces 44 of the interposer body 38 of each of the first and second segments 36a, 36b being exposed in and substantially flush with a respective one of the side surfaces 66. Further, each of the of the lateral side surfaces 46 of the interposer body 38 of each of the first and second segments 36a, 36b is exposed in and substantially flush with a respective one of the side surfaces 66. The encapsulant material which ultimately hardens into the package body 60 under fills the leads 20 (i.e., covers the shelves 26 defined by the leads 20), thus effectively creating a mechanical interlock between the package body 60 and leads 20 embedded therein.

Referring now to FIG. 3, there is shown a pair of semiconductor packages 10 (each of which has the above-described structural attributes) as mechanically and electrically connected to each other in a stacked arrangement. To facilitate such stacking, the exposed bottom surfaces 24 of the leads 20 of each set within the upper semiconductor package 10 of the stack are electrically connected to respective ones of the exposed top pads 48 of a corresponding one of the first and second segments 36a, 36b of the laminate interposer 36 embedded in the package body 60 of the lower semiconductor package 10 in the stack. Such electrical connection is preferably facilitated through the use of solder layers 68, each of which is captured between one of the top pads 48 of the lower semiconductor package 10 of the stack and the bottom surfaces 24 of respective ones of the leads 20 of the upper semiconductor package 10 of the stack. Though only two semiconductor packages 10 are depicted in FIG. 3 as being stacked upon each other, those of ordinary skill in the art will recognize that the configuration of each of the semiconductor packages 10 allows for the assembly of stacks including more than two semiconductor packages 10. Additionally, if a stack is to be formed including only the two semiconductor packages 10 shown in FIG. 3, it will be recognized that the top semiconductor package 10 in the stack could be modified so as to eliminate the embedded interposer 36.

As indicated above, in the semiconductor package 10 of the first embodiment, two sets of the leads 20 are provided, with the leads 20 of each set extending along a respective one of an opposed pair of the side surfaces 66 defined by the package body 60. Additionally, as is apparent from the number of exposed top pads 48 included in each of the first and second segments 36a, 36b as depicted in FIG. 1, thirteen leads 20 are included in each set. However, those of ordinary skill in the art will recognize that fewer or greater than thirteen leads 20 (and hence fewer or greater than thirteen top pads 48 in each of the first and second segments 36a, 36b of the laminate interposer 36) may be included in each set thereof without departing from the spirit and scope of the present invention. Additionally, it is further contemplated that the leads 20 may be segregated into greater or fewer than the two sets shown in FIG. 1, and may be arranged so as to extend along one or more of the side surfaces 66 defined by the package body 60 in any combination. As will be recognized, if the leads 20 are arranged as a single set extending along only a single side surface 66 of the package body 60, such semiconductor package may include a laminate interposer 36 having only one of the above-described first and second segments 36a, 36b. Alternatively, if multiple sets of the leads 20 are provided so as to extend along respective ones of each of the side surfaces 66 of the body 60, the laminate interposer 36 may be formed to have a continuous, ring-like or frame-like configuration.

Referring now to FIG. 4, there is depicted a semiconductor package 100 constructed in accordance with a second embodiment of the present invention. The semiconductor package 100 comprises a laminate substrate 112 which has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the substrate 112 defines a generally planar top surface 116, and an opposed, generally planar bottom surface 118. Disposed in the approximate center of the top surface 116 of the substrate 112 is a generally quadrangular die pad 120 thereof. Also disposed on the top surface 116 is a plurality of top contacts 122 of the substrate 112. In the substrate 112, the contacts 122 are segregated into two sets, with the contacts 122 of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the die pad 120. Formed on the bottom surface 118 of the substrate 112 is a plurality of bottom contacts 124. In the semiconductor package 100, the top and bottom contacts 122, 124 are preferably segregated into multiple pairs, with the top contact 122 of each pair being disposed in spaced, substantial vertical alignment with the bottom contact 124 of the same pair. Though not shown, the top and bottom contacts 122, 124 of each pair are electrically connected to each other by conductive vias which extend through the substrate 112. However, those of ordinary skill in the art will recognize that each top contact 122 may be electrically connected to one or more bottom contacts 124 other than for the bottom contact 124 in vertical alignment therewith. Further, the top and bottom contacts 122, 124 of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is any conductive via extending therebetween.

Attached to the die pad 120 of the substrate 112 is a die stack 128 of the semiconductor package 100. The die stack 128 comprises a plurality of individual semiconductor dies 130 which are arranged in a stacked configuration. In this regard, each of the semiconductor dies 130 in the die stack 128 is secured to the semiconductor die 130 below it by a layer 132 of a suitable adhesive. Similarly, the attachment of the lowermost semiconductor die 130 in the die stack 128 to the die pad 120 is facilitated by an additional adhesive layer 132. As shown in FIG. 4, four semiconductor dies 130 are depicted as being included in the die stack 128. However, those of ordinary skill in the art will recognize that the die stack 128 may be assembled to include fewer or greater than the four semiconductor 130 dies depicted in FIG. 4. In the semiconductor package 100, the pads or terminals of each of the semiconductor dies 130 of the die stack 128 are electrically connected to the top contacts 122 through the use of conductive wires 134. The conductive wires 134 may be fabricated from aluminum, copper, gold, silver or a functional equivalent. Though not shown in FIG. 4, it is contemplated that that lowermost one of the semiconductor dies 130 in the stack thereof may be electrically connected to the underlying substrate 122 through the use of a flip-chip connection as an alternative to the use of the wires 134.

The semiconductor package 100 further comprises a laminate interposer 136 which is mounted and electrically connected to the top contacts 122 of the substrate. As seen in FIG. 4, the interposer 136 comprises a first segment 136a which is electrically connected to each of the top contacts 122 of one of the sets thereof, and a separate second segment 136b which is electrically connected to each of the top contacts 122 of the remaining set thereof. The first and second segments 136a, 136b of the interposer 136 are identically configured to each other and, in the completed semiconductor package 100, extend in spaced, generally parallel relation to each other.

Each of the interposer segments 136a, 136b of the interposer 136 comprises an interposer body 138 having a top surface 140, a bottom surface 142, an opposed pair of longitudinal side surfaces 144, and an opposed pair of lateral side surfaces. Embedded within the interposer body 138 of each of the first and second segments 136a, 136b is a plurality of top pads 148. Additionally, disposed on the bottom surface 142 of the interposer body 138 of each of the first and second segments 136a, 136b is a plurality of bottom pads 150. The top and bottom pads 148, 150 of each of the first and second segments 136a, 136b are segregated into multiple pairs, with the top pad 148 of each pair being disposed in spaced, substantial vertical alignment with the bottom pad 150 of the same pair. As seen in FIG. 4, the top and bottom pads 148, 150 of each pair within each of the first and second segments 136a, 136b are electrically connected to each other by one or more conductive vias 152 which extend through the interposer body 138 substantially perpendicularly between the top and bottom pads 148, 150 of the corresponding pair. The top and bottom pads 148, 150 of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s) 152 extending therebetween. Those of ordinary skill in the art will recognize that the top and bottom pads 148, 150 of each pair need not necessarily be in exact vertical alignment, and that some degree of juxtaposition therebetween is contemplated to fall within the scope of the present invention.

Formed in the top surface 140 of the interposer body 138 of each of the first and second segments 136a, 136b of the laminate interposer 136 is a plurality of circularly configured top openings 154. Exposed within each of the top openings 154 is a respective one of the top pads 148. In the semiconductor package 100, each bottom pad 150 in each of the first and segments 136a, 136b is electrically connected to a respective one of the top contacts 122 of the corresponding set thereof by a solder ball 158. As best seen in FIG. 4, such attachment is preferably facilitated such that one of the longitudinal side surfaces 144 of each of the first and second segments 136a, 136b extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the substrate 112. Formed on each of the bottom contacts of the substrate 122 is a solder bump 168, the use of which will be described in more detail below.

In the semiconductor package 100, the die stack 128, wires 134, and portions of the substrate 112 and first and second segments 136a, 136b of the laminate interposer 136 are encapsulated or covered by an encapsulant material which, upon hardening, forms a package body 160 of the semiconductor package 100. Also fully covered by the package body 160 are the solder balls 158 used to effectuate the electrical connection between the first and second segments 136a, 136b of the laminate interposer 136 and the first and second sets of top contacts 122 of the substrate 112. The fully formed package body 160 has a generally quadrangular configuration and defines a generally planar top surface 162 and an opposed, generally planar bottom surface which contacts the top surface 116 of the substrate 112. The package body 160 also defines multiple side surfaces 166. The package body 160 is preferably formed such that the bottom surface 118 of the substrate 112 is not covered thereby. The package body 160 is further formed such that the top surface 140 of the interposer body 138 of each of the first and second segments 136a, 136b is exposed in and substantially flush with the top surface 162, with one of the longitudinal side surfaces 144 of the interposer body 138 of each of the first and second segments 136a, 136b being exposed in and substantially flush with a respective one of the side surfaces 166. Further, each of the of the lateral side surfaces of the interposer body 138 of each of the first and second segments 136a, 136b is exposed in and substantially flush with a respective one of the side surfaces 166.

Referring now to FIG. 5, there is shown a pair of semiconductor packages 100 (each of which has the above-described structural attributes) as mechanically and electrically connected to each other in a stacked arrangement. To facilitate such stacking, the solder bumps 168 formed on the exposed portions of bottom contacts 124 of each set within the upper semiconductor package 100 of the stack are electrically connected to respective ones of the exposed top pads 148 of a corresponding one of the first and second segments 136a, 136b of the laminate interposer 136 embedded in the package body 160 of the lower semiconductor package 100 in the stack. Such electrical connection is preferably facilitated through the reflow of the solder bumps 168. Though only two semiconductor packages 100 are depicted in FIG. 5 as being stacked upon each other, those of ordinary skill in the art will recognize that the configuration of each of the semiconductor packages 100 allows for the assembly of stacks including more than two semiconductor packages 100. Additionally, if a stack is to be formed including only the two semiconductor packages 100 shown in FIG. 5, it will be recognized that the top semiconductor package 100 in the stack could be modified so as to eliminate the embedded interposer 136.

As indicated above, in the semiconductor package 100 of the second embodiment, two sets of the top contacts 122 are provided on the substrate 112, with the top contacts 122 of each set extending along a respective one of an opposed pair of the side surfaces 166 defined by the package body 160. The top plan view of the completed semiconductor package 100 is identical to that of the semiconductor package 10 as shown in FIG. 1. However, it is contemplated that the top contacts 122 may be segregated into greater or fewer than the two sets, and may be arranged so as to extend along one or more of the side surfaces 166 defined by the package body 160 in any combination. As will be recognized, if the top contacts 122 are arranged as a single set extending along only a single side surface 166 of the package body 160, such semiconductor package may include a laminate interposer 136 having only one of the above-described first and second segments 136a, 136b. Alternatively, if multiple sets of the top contacts 122 are provided so as to extend along respective ones of each of the side surfaces 166 of the body 160, the laminate interposer 136 may be formed to have a continuous, ring-like or frame-like configuration.

Referring now to FIG. 6, there is depicted a chip stack comprising a stacked pair of identically configured semiconductor packages 200, the electrical connection between the stacked semiconductor packages 200 being effectuated by a laminate interposer 236. Each of the semiconductor packages 200 comprises a leadframe 212 which itself includes a die attach pad or die pad 214. The die pad 214 has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the die pad 214 defines a generally planar top surface 216, and an opposed, generally planar bottom surface 218.

In addition to the die pad 214, the leadframe 212 of each of the semiconductor packages 200 comprises a plurality of leads 220. The leads 220 of each semiconductor package 200 are segregated into two sets, with the leads 220 of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the die pad 214. Each lead 220 preferably defines a generally planar top surface 222, and a generally planar bottom surface 224 which is disposed in opposed relation to the top surface 222. In addition to the top and bottom surfaces 222, 224, each lead 220 further defines a shoulder or shelf 226 which is recessed relative to the bottom surface 224, and extends in opposed relation to the top surface 222. The shelf 226 of each lead 220 also extends to the innermost end thereof, i.e., the end disposed closest to the die pad 214.

The leadframe 212 of each semiconductor package 200 is preferably fabricated from a conventional metal material, such as copper or copper alloy. The formation of the shelves 226 within the leads 220 and the top surface 216 of the die pad 214 is preferably facilitated by subjecting a metal plate from which the leadframe 212 is typically formed to a partial etching process. More particularly, each of the opposed, generally planar faces or sides of such metal plate preferably has an etch mask applied thereto in a manner wherein the subsequent application of a suitable etchant to the metal plate will effectively remove metal material therefrom as facilitates the formation of the top surface 216 of the die pad 214 and the recessed shelves 226 of the leads 220. Such etching process may also be used to facilitate the formation of the die pad 214 and leads 220 themselves from the original metal plate, or may be implemented so as to facilitate the formation of the top surface 216 and shelves 226 subsequent to the die pad 214 and leads 220 being defined by the completion of a stamping process upon the original metal plate.

As is further seen in FIG. 6, the partial etching process to which the die pad 214 and leads 220 are subjected is preferably completed in a manner wherein the thickness of the die pad 214 between the top and bottom surfaces 216, 218 thereof is approximately one-half of the thickness of each of the leads 220 between the top and bottom surfaces 222, 224 thereof. Similarly, the thickness of each lead 220 between the top surface 222 and the shelf 226 thereof is approximately one-half of the thickness of each lead 220 between the top and bottom surfaces 222, 224 thereof. Thus, in the leadframe 212, the bottom surfaces 218, 224 of the die pad 214 and leads 220 extend in generally co-planar relation to each other. Though the top surface 216 of the die pad 214 and the shelves 226 of the leads 220 are typically not perfectly planar due to their formation as a result of the completion of a chemical etching process, such surfaces also extend in generally co-planar relation to each other in the manner shown in FIG. 6.

Attached to the top surface of the die pad 214 is a die stack 228 of the semiconductor package 200. The die stack 228 comprises a plurality of individual semiconductor dies 230 which are arranged in a stacked configuration. In this regard, each of the semiconductor dies 230 in the die stack 228 is secured to the semiconductor die 230 below it by a layer 232 of a suitable adhesive. Similarly, the attachment of the lowermost semiconductor die 230 in the die stack 228 to the die pad 214 is facilitated by an additional adhesive layer 232. As shown in FIG. 6, four semiconductor dies 230 are depicted as being included in the die stack 228. However, those of ordinary skill in the art will recognize that the die stack 228 may be assembled to include fewer or greater than the four semiconductor dies 230 depicted in FIG. 6. In each semiconductor package 200, the pads or terminals of each of the semiconductor dies 230 of the corresponding die stack 228 are electrically connected to the leads 220 through the use of conductive wires 234. The conductive wires 234 may be fabricated from aluminum, copper, gold, silver or a functional equivalent.

In each semiconductor package 200, the die stack 228, wires 234, and portions of the die pad 214 and leads 220 are encapsulated or covered by an encapsulant material which, upon hardening, forms a package body 260 of the semiconductor package 200. The fully formed package body 260 has a generally quadrangular configuration and defines a generally planar top surface 262 and an opposed, generally planar bottom surface 264. In addition to the top and bottom surfaces 62, 64, the package body 60 also defines multiple, sloped or tapered side surfaces 266. The package body 260 is preferably formed such that the bottom surfaces 218, 224 of the die pad 214 and leads 220 are each exposed in and substantially flush with the bottom surface 264. The package body 260 is further formed such that portions of the leads 220 protrude from respective side surfaces 266, thus resulting in portions of the top surfaces 222 of the leads 220 not being covered by the package body 260 and thus exposed in the semiconductor package 200. The encapsulant material which ultimately hardens into the package body 260 under fills the leads 220 (i.e., covers the shelves 226 defined by the leads 220), thus effectively creating a mechanical interlock between the package body 260 and leads 220 embedded therein.

In the chip stack shown in FIG. 6, the upper and lower semiconductor packages 200 are electrically and mechanically connected to each other by a laminate interposer 236 which is mounted and electrically connected to the exposed portions of the top surfaces 222 of the leads 220 of the lower semiconductor package 200 of the stack and to the bottom surfaces 224 of the leads 220 of the upper semiconductor package 200 of the stack. The interposer 236 comprises a first segment 236a which is electrically connected to each of the leads 220 of one of the sets included in each of the semiconductor packages 200, and a separate second segment 236b which is electrically connected to each of the leads 220 of the remaining set included in each of the semiconductor packages 200. The first and second segments 236a, 236b of the interposer 236 are identically configured to each other and, in the chip stack, extend in spaced, generally parallel relation to each other.

Each of the interposer segments 236a, 236b of the interposer 236 comprises an interposer body 238 having a top surface 240, a bottom surface 242, an opposed pair of longitudinal side surfaces 244, and an opposed pair of lateral side surfaces. Disposed on the top surface 240 of the interposer body 238 of each of the first and second segments 236a, 236b is a plurality of top pads 248. Additionally, disposed on the bottom surface 242 of the interposer body 238 of each of the first and second segments 236a, 236b is a plurality of bottom pads 250. The top and bottom pads 248, 250 of each of the first and second segments 236a, 236b are segregated into multiple pairs, with the top pad 248 of each pair being disposed in spaced, substantial vertical alignment with the bottom pad 250 of the same pair. As seen in FIG. 6, the top and bottom pads 248, 250 of each pair within each of the first and second segments 236a, 236b are electrically connected to each other by one or more conductive vias 252 which extend through the interposer body 238 substantially perpendicularly between the top and bottom pads 248, 250 of the corresponding pair. The top and bottom pads 248, 250 of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s) 252 extending therebetween.

To facilitate the formation of the chip stack shown in FIG. 6, the exposed portions of the top surfaces 222 of the leads 220 of each set within the lower semiconductor package 200 of the stack are electrically connected to respective ones of the bottom pads 250 of a corresponding one of the first and second segments 236a, 236b of the laminate interposer 236. Such electrical connection is preferably facilitated through the use of solder layers 268. Similarly, the exposed bottom surfaces 224 of the leads 220 of each set within the upper semiconductor package 200 of the stack are electrically connected to respective ones of the top pads 248 of a corresponding one of the first and second segments 236a, 236b of the laminate interposer 236 through the use of the solder layers 268. In order to improve reliability, the bottom surface 264 of the package body 260 and/or the bottom surface 218 of the die pad 214 of the top semiconductor package 200 in the stack may be adhesively attached to the top surface 262 of the package body 260 of the bottom semiconductor package 200 in the stack through the use of an adhesive. Because the exposed bottom surface 218 of the die pad 214 typically has a surface finish that is not compatible with adhesives, a half etched region may be added into the bottom surface 218 of the die pad 214 in each semiconductor package 200 to provide an area that will be compatible with adhesive materials. The same holds true in relation to the bottom surface 18 of the die pad 14 of the semiconductor package 10 shown in FIGS. 2 and 3. Though only two semiconductor packages 200 are depicted in FIG. 6 as being stacked upon each other, those of ordinary skill in the art will recognize that the configuration of each of the semiconductor packages 200 allows for the assembly of stacks including more than two semiconductor packages 200.

As indicated above, in each of the semiconductor package 200, two sets of the leads 220 are provided, with the leads 220 of each set extending along a respective one of an opposed pair of the side surfaces 266 defined by the package body 260. However, those of ordinary skill in the art will recognize that the leads 220 may be segregated into greater or fewer than the two sets, and may be arranged so as to extend along one or more of the side surfaces 266 defined by the package body 260 in any combination. As will be recognized, if the leads 220 are arranged as a single set extending along only a single side surface 266 of the package body 260, the chip stack may include a laminate interposer 236 having only one of the above-described first and second segments 236a, 236b. Alternatively, if multiple sets of the leads 220 are provided so as to extend along respective ones of each of the side surfaces 266 of the body 260, the laminate interposer 236 integrated into the chip stack may be formed to have a continuous, ring-like or frame-like configuration.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.