Semiconductor device having through electrodes protruding from dielectric layer

Description

TECHNICAL FIELD

One embodiment relates to a semiconductor device and a manufacturing method thereof.

BACKGROUND

In pace with consumers' demands, a recent trend in the information technology (IT) industry is moving toward compactness and convenience, and semiconductor devices have been continuously required to be more miniaturized or designed into modules accordingly. Such changes have resulted in development of device fabrication techniques and require further advanced processing technology.

A typical exemplary semiconductor device satisfying such a new trend is an SIP (System In Package), in which semiconductor dies each having a characteristic function are packaged into a single device, or multiple devices are stacked and fabricated into modules.

Recently, in order to stack the same or different semiconductor dies, which is an essential process for the SIP technology, a chiefly researched process is a TSV (Through-Silicon-Vias) process, in which semiconductor dies are interconnected in a longitudinal direction by forming through-holes on a silicon wafer. Here, known techniques of forming through-holes for the TSV include laser drilling, wet etching, dry etching, and so on.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment;

FIG. 2 is a flowchart of a manufacturing method of a semiconductor device according to another embodiment; and

FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J are cross-sectional views of the manufacturing method of the semiconductor device according to another embodiment.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.

DETAILED DESCRIPTION

Referring to FIG. 1, a cross-sectional view of a semiconductor device 100 according to one embodiment is illustrated.

As illustrated in FIG. 1, the semiconductor device 100 includes a semiconductor die 110, an insulation layer 120, a through electrode 130, and a dielectric layer 140.

The semiconductor die 110 includes a first surface 111 having an approximately planar shape, a second surface 112, opposite to the first surface 111 and having an approximately planar shape, a conductive pad 113 formed on the second surface 112, and a through-hole 114 formed through the first surface 111 and the conductive pad 113. Here, the conductive pad 113 may be any one selected from a common bond pad, a redistribution layer, and equivalents thereof, but the kind of the conductive pad 113 is not limited to that illustrated herein. In addition, the semiconductor die 110 includes an active region (not shown) having a plurality of circuit devices and circuit patterns formed therein. Further, an inactive region is formed outside the active region, and the through-hole 114 is formed in the inactive region that does not affect operations of circuit devices or the circuit patterns. In addition, the active region is electrically connected to the conductive pad 113.

The insulation layer 120 is formed on an inner wall of the through-hole 114. That is to say, the insulation layer 120 is formed on the inner wall of the through-hole 114 formed through the first surface 111 and the conductive pad 113 to a predetermined thickness. The insulation layer 120 prevents the through electrode 130 from being shorted to the active region or the inactive region of the semiconductor die 110, i.e., the insulation layer 120 electrically isolates the through electrode 130 from the bulk of the semiconductor die 110. The insulation layer 120 may be any one selected from silicon oxide, silicon nitride, a polymer, and equivalents thereof, but the kind of the insulation layer 120 is not limited to that illustrated herein.

The through electrode 130 is formed inside the insulation layer 120, while upwardly protruding a predetermined length from the first surface 111 of the semiconductor die 110 or downwardly protruding a predetermined length from the conductive pad 113 of the semiconductor die 110. The through electrode 130 is electrically connected to the conductive pad 113. Therefore, the through electrode 130 covers a surface of the conductive pad 113. In addition, the through electrode 130 may be any one selected from copper (Cu), aluminum (Al), gold (Au), silver (Ag), and equivalents thereof, but the material of the through electrode 130 is not limited to that illustrated herein. The through electrode 130 is electrically connected to the circuit devices or the circuit patterns in the active region through the conductive pad 113. The through electrode 130 may further include a barrier or seed layer formed on the inner wall of the insulation layer 120.

The dielectric layer 140 is formed on the first surface 111 of the semiconductor die 110. The dielectric layer 140 has a thickness smaller than that of the through electrode 130 protruding through the first surface 111. Therefore, a top end 131 of the through electrode 130 is exposed to the outside or protrudes through the dielectric layer 140. In addition, the dielectric layer 140 formed outside the through electrode 130 has a curved surface 141 extending toward downward and lateral sides. The curved surface 141, which is formed in a special manufacturing process according to embodiments, serves to surround the lateral surface of the through electrode 130. Here, the dielectric layer 140 may be any one selected from a polymer and equivalents thereof, but the material of the dielectric layer 140 is not limited to that illustrated herein.

In such a manner, one embodiment provides a semiconductor device having a plurality of semiconductor dies 110 vertically stackable using the through electrode 130, not using a wire connection method. In addition, in one embodiment, since the top end 131 of the through electrode 130 is exposed to the outside or protrudes through the dielectric layer 140, it is not necessary to form a separate conductive pattern on the through electrode 130. However, in one embodiment, to enhance vertical stacking of a plurality of semiconductor dies 110, a coating, e.g., plating, is applied to top end 131 such as a nickel-gold (NiAu) plating, a nickel-palladium-gold (NiPdAu) plating, or a tin (Sn) plating or other plating.

Referring to FIG. 2, a manufacturing method of the semiconductor device 100 according to another embodiment is illustrated.

As illustrated in FIG. 2, the manufacturing method of the semiconductor device 100 according to another embodiment includes a forming through-hole operation S1, a forming insulation layer operation S2, a forming through electrode operation S3, a back grinding operation S4, an etching operation S5, a coating dielectric layer operation S6, an under exposing operation S7, a developing operation S8, a curing operation S9, and a performing plasma descum process operation S10.

Referring to FIGS. 3A through 3J, the manufacturing method of the semiconductor device 100 according to another embodiment is illustrated.

In forming through-hole operation S1, as illustrated in FIG. 3A, a through-hole 114 having a predetermined depth is formed in a semiconductor die 110 having a first surface 111, a second surface 112 and a conductive pad 113. Here, the through-hole 114 may be formed by any one process selected from laser drilling, wet etching, dry etching, and equivalents thereof, but the process of the through-hole 114 is not limited to that illustrated herein. Unlike the wet etching or the dry etching, however, the laser drilling does not require forming a mask or performing a photography process. Rather, according to the laser drilling, the depth and width of the through-hole 114 can be relatively easily set. FIG. 3A illustrates that the depth of the through-hole 114 is substantially the same as the thickness of the semiconductor die 110. In practice, however, it should be appreciated that the depth of the through-hole 114 is considerably smaller than that of the semiconductor die 110.

In forming insulation layer operation S2, as illustrated in FIG. 3B, an insulation layer 120 having a predetermined thickness is formed on an inner wall of the through-hole 114. The insulation layer 120 may be formed of silicon oxide (SiO_x) or silicon nitride (SiN_x) by chemical vapor deposition (CVD), or a polymer by spin coating or sublimation, but the formation method of the insulation layer 120 is not limited to that illustrated herein.

In forming through electrode operation S3, as illustrated in FIG. 3C, the inner wall of the through-hole 114 is filled with a conductive material to form a through electrode 130. The conductive material may be any one selected from copper (Cu), aluminum (Al), gold (Au), silver (Ag), and equivalents thereof, but the material of the conductive material is not limited to that illustrated herein.

Prior to the formation of the through electrode 130, a barrier and/or seed layer (not shown) may be formed on the inner wall of the insulation layer 120. The through electrode 130 may also be formed by plating. In addition, the through electrode 130 may be formed such that its bottom end covers the conductive pad 113, thereby allowing the through electrode 130 and the conductive pad 113 to be electrically connected to each other. Here, since the conductive pad 113 is electrically connected to the active region, the through electrode 130 is also electrically connected to the active region.

Meanwhile, the through electrode 130 is exposed to the outside through the first surface 111 of the semiconductor die 110, which is implemented by the following steps.

In back grinding operation S4, as illustrated in FIG. 3D, the first surface 111 of the semiconductor die 110 is subjected to back grinding until a top end 131 of the through electrode 130 is exposed. Since a region removed by the back grinding is an inactive region, rather than an active region, the semiconductor die 110 is not affected at all in operation even if the region is removed by the back grinding.

In etching operation S5, as illustrated in FIG. 3E, peripheral region of the through electrode 130 are etched using an etching solution or an etching gas that is not reactive with the through electrode 130 but is reactive with the semiconductor die 110 and the insulation layer 120. As a result, the through electrode 130 protrudes a predetermined length to the outside through the first surface 111 of the semiconductor die 110.

In coating dielectric layer operation S6, as illustrated in FIG. 3F, the dielectric layer 140 is coated on the first surface 111 of the semiconductor die 110 to a thickness enough to cover the through electrode 130. The dielectric layer 140 is formed by, for example, spin coating, but the coating method of the dielectric layer 140 is not limited to that illustrated herein. Here, the dielectric layer 140 may be a photopolymer. Upon being exposed to UV radiation, the photopolymer may be removed by developing.

In under exposing operation S7, as illustrated in FIG. 3G, an under exposure dose, which is smaller than an appropriate exposure dose, is applied onto a surface of the dielectric layer 140. Here, the exposure dose (H) refers to a total energy quantity of UV radiation received by the dielectric layer 140 that is sensitive to the UV radiation, and may be expressed as intensity (I) of light applied to the dielectric layer 140 (brightness) multiplied by an exposure time (t), i.e., H=I*t, where ‘H’ denotes an exposure dose, ‘I’ denotes light intensity, and ‘t’ denotes an exposure time, respectively.

In addition, the appropriate exposure dose refers to a minimum exposure dose required to completely remove the dielectric layer 140 from the first surface 111 of the semiconductor die 110 assuming that the developing of the dielectric layer 140 is performed at a preset temperature for a preset time. Stated another way, the appropriate exposure dose is the exposure dose which will result in the complete removal of the dielectric layer 140 during developing. The under exposure dose refers to a low dosage that is insufficient to reach the appropriate exposure dose, so that some of the dielectric layer 140 will remain on the first surface 111 of the semiconductor die 110 even when the dielectric layer 140 is developed at a preset temperature for a preset time, i.e., is developed such that the dielectric layer 140 would be completely removed with the appropriate exposure dose.

The under exposure dose for the dielectric layer 140 may vary according to the kind and thickness of the dielectric layer 140. Therefore, previous experiments are carried out many times with kinds and thicknesses of the dielectric layer 140 varying, thereby obtaining the under exposure dose for seeking a desired thickness of the remaining dielectric layer 140.

In addition, under exposing operation S7 may be performed over the entire wafer having a plurality of semiconductor dies without using a mask. Therefore, the cost required in the conventional process using masks can be reduced, and the overall manufacturing process can be considerably simplified.

Further, under exposing operation S7 may not be necessarily performed. That is to say, developing operation S8 may be performed immediately after coating dielectric layer operation S6, without performing under exposing operation S7. In this case, appropriate processing parameters are necessary to develop only a region of the dielectric layer 140 for removal.

In developing operation S8, as illustrated in FIG. 3H, the developing is performed using a general developing solution, thereby removing a partially removed region of the dielectric layer 140. A thickness of the dielectric layer 140 remaining, sometimes called a remaining dielectric layer 140, by developing operation S8 is equal to or greater than a thickness of the through electrode 130 protruding through the first surface 111. Of course, as the result of the developing, a top end 131 of the through electrode 130 may be exposed or protrude to the outside of the dielectric layer 140.

In curing operation S9, as illustrated in FIG. 3I, heat of approximately 100˜400° C. is supplied to the remaining dielectric layer 140, thereby curing the dielectric layer 140 to make the same hardened.

In performing plasma descum process operation S10, as illustrated in FIG. 3J, plasma is supplied to remove the dielectric layer 140 remaining on the top end 131 of the through electrode 130. The plasma slightly etches the dielectric layer 140 remaining on the top end 131 and peripheral edges of the through electrode 130. In addition, in the performing of the plasma descum process, a curved surface 141 having a gradually decreasing thickness is formed on the dielectric layer 140 positioned on the peripheral edges of the through electrode 130. Stated another way, the curved surface 141 surrounds the through electrode 130 such that the thickness of the dielectric layer 140 is greatest at the through electrode 130 and decreases away from the through electrode 130 as demonstrated by the curved surface 141. Optionally, in one embodiment, to enhance vertical stacking of a plurality of semiconductor dies 110, a coating, e.g., plating, is applied to top end 131 such as a nickel-gold (NiAu) plating, a nickel-palladium-gold (NiPdAu) plating, or a tin (Sn) plating or other plating. The coating on top end 131 can also be applied at earlier stages during fabrication or omitted altogether.

As described above, in the semiconductor device 100 according to embodiments, the through electrode 130 can be formed using existing wafer bumping equipment and materials without costly equipment. In addition, in the semiconductor device 100 according to embodiments, since a photolithography process is utilized, the dielectric layer 140 and the through electrode 130, whose surfaces are very clean, can be obtained. Further, the semiconductor device 100 according to embodiments can be manufactured with considerably reduced costs.

Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.