Backside warpage control structure and fabrication method

Description

TECHNICAL FIELD

The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.

BACKGROUND

In a typical Wafer Level Chip Scale Package (WLCSP), the pattern of bond pads on the active surface of an electronic component is redistributed to a pattern of frontside terminals for electrical connection to other structures. This frontside redistribution structure includes a circuit pattern and a plurality of dielectric layers on the active surface of the electronic component.

However, the frontside redistribution structure has a thermal coefficient of expansion (TCE) different than the silicon of the electronic component. This mismatch in TCEs causes the frontside redistribution structure to exert stress on the electronic component. This stress, in turn, causes undesirable warpage of the electronic component.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a backside warpage control structure fabrication method in accordance with one embodiment;

FIG. 2 is a cross-sectional view of an array including a substrate including a plurality of electronic components in accordance with one embodiment;

FIG. 3 is a cross-sectional view of the array of FIG. 2 at a later stage during fabrication in accordance with another embodiment;

FIGS. 4 and 5 are cross-sectional views of the array of FIG. 3 at later stages during fabrication in accordance with various embodiments;

FIG. 6 is a cross-sectional view of the array of FIG. 3 at a later stage during fabrication in accordance with another embodiment;

FIGS. 7 and 8 are cross-sectional views of the array of FIG. 6 at later stages during fabrication in accordance with various embodiments;

FIGS. 9, 10, 11 are top plan views of the array including a backside warpage control structure of FIG. 5 in accordance with one embodiment.

In the following description, the same or similar elements are labeled with the same or similar reference numbers.

DETAILED DESCRIPTION

As an overview and in accordance with one embodiment, referring to FIG. 5, an array 200 includes a substrate 202 having a frontside surface 206 and a backside surface 342. Through vias 218 extend through substrate 202 between frontside surface 206 and backside surface 342, through vias 218 comprising active surface ends 222 at frontside surface 206.

A frontside redistribution structure 224 formed on frontside surface 206 and is coupled to active surface ends 222. Frontside redistribution structure 224 exerts force on frontside surface 206, e.g., due to a difference in the thermal coefficient of expansion (TCE) between frontside redistribution structure 224 and substrate 202.

To prevent warpage of substrate 202, a backside warpage control structure 462 is coupled to backside surface 342 of substrate 202. Backside warpage control structure 462 exerts an equal but opposite force to the force exerted by the frontside redistribution structure 224 thus avoiding warpage of substrate 202.

Now in more detail, FIG. 1 is a block diagram of a backside warpage control structure fabrication method 100 in accordance with one embodiment. FIG. 2 is a cross-sectional view of an array 200 including a substrate 202 including a plurality of electronic components 204 in accordance with one embodiment.

In one embodiment, substrate 202 is a silicon wafer. Substrate 202 includes a frontside, e.g., first, surface 206 and an opposite backside, e.g., second, surface 208.

Substrate 202 includes electronic components 204 integrally connected to one another. For simplicity, the term substrate 202 shall be used herein and it is to be understood that this term generally includes electronic components 204.

In one embodiment, electronic components 204 are integrated circuit chips, e.g., active components including active circuitry. However, in other embodiments, electronic components 204 are passive components such as capacitors, resistors, or inductors.

In accordance with this embodiment, electronic components 204 include active surfaces 210 and opposite inactive surfaces 212. Active surfaces 210 and inactive surfaces 212 generally define frontside surface 206 and backside surface 208 of substrate 202, respectively. For simplicity, the terms frontside surface 206 and backside surface 208 shall be used herein and it is to be understood that these terms generally include active surfaces 210 and inactive surfaces 212, respectively. Electronic components 204 further includes bond pads 214 formed on active surfaces 210.

Electronic components 204 are delineated from one another by singulation streets 216. Substrate 202 is singulated, e.g., sawed, along singulation streets 216 to separate packaged electronic components 204 from one another at a later stage during fabrication.

In another embodiment, array 200 includes a plurality of interposers 204 connected together (instead of electronic components 204). More particularly, interposers 204, e.g., silicon interposers, have an absence of active circuitry and thus do not have bond pads 214. The structure of array 200 when formed of interposers 204 is otherwise the same or similar to the structure of array 200 when formed of electronic components as discussed above. Array 200 including electronic components 204 (instead of interposers) shall be discussed below but it is to be understood that the discussion is equally applicable to the embodiment where array 200 is formed of interposers.

Referring now to FIGS. 1 and 2 together, in a form through vias operation 102, through vias 218 are formed in electronic components 104. Through vias 218 are surrounded by dielectric through via passivation linings 220.

Illustratively, through via apertures are formed, e.g., by laser drilling, into electronic components 104 from frontside surface 206. Through via passivation linings 220, e.g., silicon oxide (SiO₂), are formed on the sidewalls of the through via apertures. In one embodiment, the silicon of substrate 202 exposed within the through via apertures is oxidized to form through via passivation linings 220. In another embodiment, a dielectric material is deposited within the through via apertures to form through via passivation linings 220.

Through vias 218 are formed within through via passivation linings 220. Illustratively, an electrically conductive material, e.g., copper or tungsten, is deposited, e.g., plated, within through via passivation linings 220 to form through vias 218. Through via passivation linings 220 electrically isolate through vias 218 from substrate 202.

Through vias 218 include active surface ends 222. Active surface ends 222 are circular in accordance with this embodiment. Active surface ends 222 are coplanar with and parallel to frontside surface 206 of substrate 202.

From form through vias operation 102, flow moves to a form frontside redistribution structure operation 104. In form frontside redistribution structure operation 104, a frontside redistribution structure 224 is formed.

In accordance with this embodiment, frontside redistribution structure 224 includes a circuit pattern 226 and frontside dielectric layers 228, 230.

More particularly, frontside dielectric layer 228, sometimes called a first frontside dielectric layer, is formed on frontside surface 206 of substrate 202. In one embodiment, frontside dielectric layer 228 is a passivation layer formed on frontside surface 206 as provided from the manufacture of substrate 202, e.g., the wafer manufacturer. In another embodiment, frontside dielectric layer 228 is applied to frontside surface 206, e.g., is a separate layer of polyimide or other dielectric material that is applied to frontside surface 206.

Frontside dielectric layer 228 has via apertures 232 formed therein that exposed bond pads 214 and/or active surface ends 222 of through vias 218. Circuit pattern 226, e.g., copper or other electrically conductive material, includes electrically conductive vias 234 formed within via apertures 232. Vias 234 are in contact with and electrically connected to bond pads 214 and/or active surface ends 222 of through vias 218.

Circuit pattern 226 further includes traces 236, e.g., long thin connectors extending parallel to frontside surface 206. Traces 236 are formed on or embedded within frontside dielectric layer 228.

Traces 236 terminate in frontside terminals 238, sometimes called lands, of circuit pattern 226. Frontside dielectric layer 230, sometimes called a second frontside dielectric layer 230, is formed on circuit pattern 226 and frontside dielectric layer 228. In one embodiment, frontside dielectric layer 230 is a solder mask or other dielectric material.

Frontside dielectric layer 230 is patterned to form terminal openings 240 therein. Terminal openings 240 expose frontside terminals 238 of circuit pattern 226.

Generally, frontside redistribution structure 224 redistributes the pattern of bond pads 214 and/or active surface ends 222 to the pattern of frontside terminals 238. Although circuit pattern 226 is illustrated as a single layer conductor layer between frontside dielectric layers 228, 230, generally, frontside redistribution structure 224 includes multiple conductor layers and multiple dielectric layers. For example, frontside redistribution structure 224 includes seven conductor layers and associated dielectric layers in other embodiments.

Frontside redistribution structure 224 has a thermal coefficient of expansion (TCE) different than substrate 202 including electronic components 204. For example, frontside redistribution structure 224 includes copper and substrate 202 includes silicon, which have substantially different TCEs.

This mismatch in TCEs causes frontside redistribution structure 224 to exert stress on substrate 202 including electronic components 204. Absent a backside warpage control structure in accordance with one embodiment as discussed below, this stress would cause undesirable warpage of substrate 202 including electronic components 204.

FIG. 3 is a cross-sectional view of array 200 of FIG. 2 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 2, and 3 together, from form frontside redistribution structure operation 104, flow moves to an expose through via nubs operation 106. In expose through via nubs operation 106, through via nubs 340 of through vias 218 are exposed.

In one embodiment, substrate 202 is thinned, sometimes called backgrinded, to expose through vias 218 at backside surface 208 of substrate 202. Backside surface 208 of substrate 202 is then blanket etched, i.e., removed, to expose through via nubs 340 of through vias 218. In one embodiment, backside surface 208 is removed using a selective etch that etches substrate 202, e.g., silicon, but does not etch through vias 218, e.g., copper. Optionally, the portion of through via passivation lining 220 covering the sides of through via nubs 340 is also removed.

Generally, in expose through via nubs operation 106, substrate 202 is thinned from backside surface 208. Stated another way, a portion of substrate 202 at backside surface 208 as illustrated in FIG. 2 is removed to form a recessed backside surface 342 as illustrated in FIG. 3. For example, a Si dry etch is performed to thin substrate 202.

Accordingly, after performance of expose through via nubs operation 106, substrate 102 includes a recessed backside surface 342. Inactive surfaces 212 generally define recessed backside surface 342. For simplicity, the term recessed backside surface 342 shall be used herein and it is to be understood that this term generally includes inactive surfaces 212.

However, through vias 218 are not thinned and thus through via nubs 340 are exposed as illustrated in FIG. 3. Through vias 218 are sometimes said to stand proud of or extend from recessed backside surface 342.

Through via nubs 340 are the upper portions of through vias 218 exposed and uncovered by substrate 202. Through via nubs 340 are cylindrical protrusions protruding upwards from recessed backside surface 342.

Through via nubs 340, e.g., first portions of through vias 218, include inactive surface ends 344, e.g., planar circular ends or curved ends. Inactive surface ends 344 are spaced above recessed backside surface 342.

Generally, through vias 218 are electrically conductive columns extending between active surface ends 222 and inactive surface ends 344.

In another embodiment, to expose through via nubs 340, substrate 202 is thinned, sometimes called backgrinded, to almost expose through vias 218 at backside surface 208 of substrate 202. More particularly, through vias 218 remain enclosed within substrate 202 at backside surface 208 in accordance with this embodiment. More particularly, except at frontside surface 206, through vias 218 are totally enclosed within through via passivation linings 220. Further, a portion of substrate 202, e.g., silicon, remains between through vias 218 and backside surface 208.

Backside surface 208 of substrate 202 is then blanket etched, i.e., removed, to expose through via nubs 340 of through vias 218. In one embodiment, backside surface 208 is removed using a selective etch that etches substrate 202, e.g., silicon, but does not etch through vias 218, e.g., copper. Then a selective etch to remove through via passivation linings 220, e.g., silicon oxide, exposed from recessed backside surface 342 is performed resulting in the structure as illustrated in FIG. 3. In accordance with this embodiment, inactive surface ends 344 may not be planar but may be curved surfaces.

From expose through via nubs operation 106, flow moves to an apply backside passivation layer operation 108. In apply backside passivation layer operation 108, a backside passivation layer 346 is applied to recessed backside surface 342.

Backside passivation layer 346, sometimes called an insulation layer, includes a lower, e.g., first, passivation layer surface 348 directly attached to recessed backside surface 342. Backside passivation layer 346 further includes an opposite upper, e.g., second, passivation layer surface 350. Backside passivation layer 346 is a dielectric material.

In one embodiment, backside passivation layer 346 is formed from an organic material such as polyimide (PI), polybutyloxide (PBO), benzocyclobutene (BCB), a polymer, or other carbon containing material. In one embodiment, backside passivation layer 346 is formed by spinning, or spraying an organic material onto recessed backside surface 342 or applying a laminated film. In other embodiments, backside passivation layer 346 is an inorganic material, e.g., silicon oxide or silicon nitride, formed using a plasma enhanced chemical vapor deposition (PECVD) deposition process.

Backside passivation layer 346 is patterned to expose inactive surface ends 344 of through vias 218.

From apply backside passivation layer operation 108, flow moves to an apply seed layer operation 110. In apply seed layer 110, a seed layer 352 is applied to upper passivation layer surface 350 of backside passivation layer 346 and inactive surface ends 344 of through vias 218. Seed layer 352 is an electrically conductive material which is blanket applied, e.g., by sputtering, or other application technique. Seed layer 352 is sometimes called an under bump metal (UBM).

FIG. 4 is a cross-sectional view of array 200 of FIG. 3 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 4 together, from apply seed layer 110, flow moves to an apply mask operation 112.

In apply mask operation 112, a patterned mask 454 is applied to seed layer 352. In one embodiment, a resist is applied and patterned, e.g., using photolithography or laser ablation, to form patterned mask 454. In one specific embodiment, a photoresist is applied and a mask, e.g., formed of glass or mylar, is used to image a pattern of the photoresist to form patterned mask 454. Patterned mask 454 includes backside terminal artifacts 456 and warpage control structure artifact 458, i.e., patterned openings in patterned mask 454.

In one embodiment, backside terminal artifacts 456 are openings, e.g., a circular, rectangular, or other shaped opening, formed in patterned mask 454. Backside terminal artifacts 456 are openings extending though patterned mask 454 to expose seed layer 352 above inactive surface end 344 of through vias 218.

Warpage control structure artifact 458 is one or more openings formed in patterned mask 454. The pattern of warpage control structure artifact 458 depends upon the desired backside warpage control structure to be plated as discussed further below.

From apply mask operation 112, flow moves to a form backside terminals operation 114 and a form backside warpage control structure operation 116. In accordance with this embodiment, form backside terminals operation 114 and form backside warpage control structure operation 116 are both simultaneously performed.

In form backside terminals operation 114, backside terminals 460 are formed within backside terminal artifacts 456. Illustratively, backside terminal artifacts 456 are filled with an electrically conductive material to form backside terminals 460. In one embodiment, copper or another conductive material is plated within backside terminal artifacts 456 using seed layer 352 as a plating electrode to form backside terminals 460. Backside terminals 460 are sometimes called pads for backside ball/via lands.

In form backside warpage control structure operation 116, backside warpage control structure 462 is formed within warpage control artifact 458. Illustratively, warpage control artifact 458 is filled with an electrically conductive material to form backside warpage control structure 462. In one embodiment, copper or another conductive material is plated within warpage control artifact 458 using seed layer 352 as a plating electrode to form backside warpage control structure 462.

Illustratively, backside terminal artifacts 456 and warpage control artifact 458 are simultaneously filled with an electrically conductive material during a single plating operation. Thus, operations 114 and 116 are performed simultaneously to simultaneously form backside terminals 460 and backside warpage control structure 462. Accordingly, backside terminals 460 and backside warpage control structure 462 are formed of the same material, e.g., copper, and have the same thickness T1. Illustratively, thickness T1 is in the range of 4-10 μm although has other values in other embodiments.

FIG. 5 is a cross-sectional view of array 200 of FIG. 4 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 4, and 5 together, from form backside terminals operation 114 and form backside warpage control structure operation 116, flow moves to a strip mask operation 118. In strip mask operation 118, patterned mask 454 is stripped, i.e., removed. Upon removal of patterned mask 454, portions of seed layer 352 that were covered by patterned mask 454 are exposed.

From strip mask operation 118, flow moves to an etch exposed seed layer portion operation 120. In etch exposed seed layer portion operation 120, the exposed portion of seed layer 352 that was exposed during performance of strip mask operation 118 is removed, e.g., using a flash etch, resulting in the structure as illustrated in FIG. 5.

As described above, backside warpage control structure 462 is formed simultaneously with backside terminals 460 using the same operations 110, 112, 116, 118, 120 that ordinarily would be performed to form backside terminals 460. Accordingly, the additional cost to form backside warpage control structure 462 is minimal.

Backside warpage control structure 462 matches the expansion and/or contraction of frontside redistribution structure 224. More particularly, as discussed above, frontside redistribution structure 224 exerts tension or compression on substrate 202 including electronic components 204, for example, due to a mismatch in TCEs between frontside redistribution structure 224 and substrate 202.

In one embodiment, frontside redistribution structure 224 exerts tension on substrate 202 by pushing the edges of substrate 202 upward relative to the center of substrate 202. Absent backside warpage control structure 462, this tension would cause the edges of substrate 202 to move upwards relative to the center of substrate 202 resulting in a smile configuration.

In contrast, in another embodiment, frontside redistribution structure 224 exerts compression on substrate 202 by pulling the edges of substrate 202 downwards relative to the center of substrate 202. Absent backside warpage control structure 462, this compression would cause the edges of substrate 202 to move downwards relative to the center of substrate 202 resulting in a cry configuration.

However, backside warpage control structure 462 exerts an equal but opposite force to the force exerted by frontside redistribution structure 224 on substrate 202 that prevents warpage of substrate 202 including electronic components 224.

More particularly, if frontside redistribution structure 224 exerts compression on substrate 202, backside warpage control structure 462 also exerts compression on substrate 202 equal to the compression exerted by frontside redistribution structure 224. However, since backside warpage control structure 462 is on recessed backside surface 342 whereas frontside redistribution structure 224 is on frontside surface 206, the equal compressive stresses are exerted on substrate 202 opposite one another. This prevents warpage of substrate 202.

In another embodiment, if frontside redistribution structure 224 exerts tension on substrate 202, backside warpage control structure 462 also exerts tension on substrate 202 equal to the tension exerted by frontside redistribution structure 224. However, since backside warpage control structure 462 is on recessed backside surface 342 whereas frontside redistribution structure 224 is on frontside surface 206, the equal tensile stresses are exerted on substrate 202 opposite one another. This prevents warpage of substrate 202, i.e., keeps substrate 202 planar.

After etch expose seed layer portion operation 120, in one embodiment, additional processing on array 200 is performed. For example, additional passivation or solder mask layers are formed. Further, array 200 is singulated along singulation streets 216 to form singulated electronic component packages.

In another embodiment, a backside warpage control structure 762 (illustrated in FIGS. 7 and 8) is formed to be thicker, thinner, and/or of a different metal than backside terminals 460. Fabrication of such a backside warpage control structure 762 is illustrated in FIGS. 6, 7, 8 and discussed below.

FIG. 6 is a cross-sectional view of array 200 of FIG. 3 at a later stage during fabrication in accordance with another embodiment. Referring now to FIGS. 1, and 6 together, from apply seed layer operation 110 as discussed above, flow moves to apply mask operation 112.

In apply mask operation 112, a patterned mask 654 is applied to seed layer 352 in a manner similar to that discussed above regarding patterned mask 454. Patterned mask 654 includes backside terminal artifacts 456, i.e., patterned openings in patterned mask 654, as described above. Patterned mask 654 is sometimes called a first patterned mask.

From apply mask operation 112, flow moves to form backside terminals operation 114. In form backside terminals operation 114, backside terminals 460 are formed within backside terminal artifacts 456 as discussed above.

FIG. 7 is a cross-sectional view of array 200 of FIG. 6 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 6, and 7 together, from form backside terminals operation 114, flow moves to strip mask operation 118. In strip mask operation 118, patterned mask 654 (FIG. 6) is stripped, i.e., removed.

From strip mask operation 118, flow returns to apply mask operation 112 as indicated by the dotted arrow at the left of FIG. 1. In apply mask operation 112, a patterned mask 754 is applied to seed layer 352 and covers and protects backside terminals 460 in a manner similar to that discussed above regarding patterned mask 454. Patterned mask 754 is sometimes called a second patterned mask.

Patterned mask 754 includes a warpage control artifact 758, i.e., a patterned opening in patterned mask 754, similar to warpage control artifact 458 as described above.

From apply mask operation 112, flow moves to form backside warpage control structure operation 116. In form backside warpage control structure operation 116, a backside warpage control structure 762 is formed within warpage control artifact 758. Illustratively, warpage control artifact 758 is filled with an electrically conductive material to form backside warpage control structure 762. In one embodiment, copper or another conductive material is plated within warpage control artifact 758 using seed layer 352 as a plating electrode to form backside warpage control structure 762.

Further, paying particular attention to FIGS. 6 and 7 together, in accordance with this embodiment, patterned mask 754 and backside warpage control structure 762 are thicker than backside terminals 460 and patterned mask 654. More particularly, patterned mask 654 and backside terminals 460 have first thickness T1 and patterned mask 754 and backside warpage control structure 762 have a second thickness T2. Thickness T2 of patterned mask 754 and backside warpage control structure 762 is greater than thickness T1 of patterned mask 654 and backside terminals 460.

FIG. 8 is a cross-sectional view of array 200 of FIG. 7 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 7, and 8 together, from form backside warpage control structure operation 116, flow moves to strip mask operation 118.

In strip mask operation 118, patterned mask 754 is stripped, i.e., removed. Upon removal of patterned mask 754, a portion of seed layer 352 that was covered by patterned mask 754 is exposed.

From strip mask operation 118, flow moves to etch exposed seed layer portion operation 120. In etch exposed seed layer portion operation 120, the exposed portion of seed layer 352 that was exposed during performance of strip mask operation 118 is removed resulting in the structure as illustrated in FIG. 8

As described above, backside warpage control structure 762 is formed after formation of backside terminals 460 in this embodiment using separate patterned masks 654, 754 and separate plating operations.

In another embodiment, backside warpage control structure 762 is formed before formation of backside terminals 460 using separate patterned masks 654, 754 and separate plating operations. In either case, this allows backside warpage control structure 762 to be formed thinner, thicker, or of a different material than backside terminals 460.

In one embodiment, as illustrated in FIG. 8, backside terminals 460 have a thickness T1 and backside warpage control structure 762 has a thickness T2. Thickness T1 is less than thickness T2, i.e., backside terminals 460 are thinner than backside warpage control structure 762.

In another embodiment, backside terminals 460 as indicated by the dashed lines have a thickness T3. Thickness T3 is greater than thickness T2, i.e., backside terminals 460 are thicker than backside warpage control structure 762.

In another embodiment, by using patterned masks 654, 754 and separate plating operations, backside warpage control structure 762 is formed of a different material than backside terminals 460. For example, backside warpage control structure 762 includes an electrically conductive material, a nonconductive material, or other type of material that is different than the material, e.g., copper, of backside terminals 460.

By using different materials and/or thicknesses of backside warpage control structure 762, backside warpage control structure 762 can be designed to match the expansion and/or contraction of frontside redistribution structure 224.

In yet another embodiment, the pattern of a backside warpage control structure such as backside warpage control structure 462 of FIG. 5 or backside warpage control structure 762 of FIG. 8 is designed to match the expansion and/or contraction of frontside redistribution structure 224. Various examples are provided below for backside warpage control structure 462 of FIG. 5 although it is to be understood that the patterns are equally applicable to backside warpage control structure 762 of FIG. 8.

FIG. 9 is a top plan view of array 200 including backside warpage control structure 462 of FIG. 5 in accordance with one embodiment. Referring now to FIG. 9, in this embodiment, backside warpage control structure 462 is formed as a full metal everywhere except spaced apart from where backside terminals 460 are formed. Stated another way, backside warpage control structure 462 is a solid metal plane with exclusion of backside terminals 460, i.e., with a backside pad exclusion rule.

FIG. 10 is a top plan view of array 200 including backside warpage control structure 462 of FIG. 5 in accordance with another embodiment. Referring now to FIG. 10, in this embodiment, backside warpage control structure 462 is formed as a cross-hatch pattern.

FIG. 11 is a top plan view of array 200 including backside warpage control structure 462 of FIG. 5 in accordance with another embodiment. Referring now to FIG. 11, in this embodiment, backside warpage control structure 462 is formed as a dot pattern, sometimes called a dot matrix.

Although particular patterns for backside warpage control structure 462 are illustrated and discussed above, generally, the pattern for backside warpage control structure 462 is selected to reduce or eliminate warpage from frontside redistribution structure 224. For example, backside warpage control structure 462 is not applied to corners of electronic components 204.

Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.